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| 20140077977 | Method and Decoder for Reconstructing a Source Signal - In a method for reconstructing a source signal, which is encoded by a set of at least two descriptions, the method comprises: receiving a subset of the set of descriptions; reconstructing a reconstructed signal at an operating bitrate of a set of operating bitrates upon the basis of the subset of descriptions, the reconstructed signal having a second probability density, wherein the second probability density comprises a first statistical moment and a second statistical moment; and manipulating the reconstructed signal, wherein the reconstructed signal is manipulated such that, irrespective of the operating bitrate, a predetermined minimum similarity between the first statistical moment of the third probability density and the first statistical moment of the first probability density and between the second statistical moment of the third probability density and the second statistical moment of the first probability density is maintained. | 03-20-2014 |
| 20150295590 | Method and Decoder for Reconstructing a Source Signal - In a method for reconstructing a source signal, which is encoded by a set of at least two descriptions, the method comprises: receiving a subset of the set of descriptions; reconstructing a reconstructed signal at an operating bitrate of a set of operating bitrates upon the basis of the subset of descriptions, the reconstructed signal having a second probability density, wherein the second probability density comprises a first statistical moment and a second statistical moment; and manipulating the reconstructed signal, wherein the reconstructed signal is manipulated such that, irrespective of the operating bitrate, a predetermined minimum similarity between a first statistical moment of a third probability density and a first statistical moment of a first probability density and between a second statistical moment of the third probability density and a second statistical moment of the first probability density is maintained. | 10-15-2015 |
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| 20130026573 | BODY CONTACT SOI TRANSISTOR STRUCTURE AND METHOD OF MAKING - The present invention puts forward a body-contact SOI transistor structure and method of making. The method comprises: forming a hard mask layer on the SOI; etching an opening exposing SOI bottom silicon; wet etching an SOI oxide layer through the opening; depositing a polysilicon layer at the opening followed by anisotropic dry etching; depositing an insulating dielectric layer at the opening followed by planarization; forming a gate stack structure by deposition and etching, and forming source/drain junctions of the transistor using ion implantation. By using the present invention, body contact for SOI field-effect transistors can be effectively formed, thereby eliminating floating-body effect in the SOI field-effect transistors, and improving heat dissipation capability of the SOI transistors and associated integrated circuits. | 01-31-2013 |
| 20130032881 | Asymmetric Source-Drain Field Effect Transistor and Method of Making - The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction. | 02-07-2013 |
| 20130270615 | METHOD FOR MAKING TRANSISTORS - A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth. | 10-17-2013 |
| 20140034955 | Nano-MOS Devices and Method of Making - The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance. | 02-06-2014 |
| 20140034956 | Asymmetric Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-06-2014 |
| 20140048875 | Asymmetrical Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-20-2014 |
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| 20110316070 | CHARGE TRAPPING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability. | 12-29-2011 |
| 20120119268 | Mixed Junction Source/Drain Field-Effect-Transistor and Method of Making the Same - The present invention is related to microelectronic technologies, and discloses specifically a mixed junction source/drain field-effect-transistor and methods of making the same. The field-effect-transistor with mixed junction source/drain comprises a semiconductor substrate, a gate structure, sidewalls, and source and drain regions having mixed junction structures, which are combinations of Schottky and P-N junctions. Compared with Schottky junction field-effect-transistors, the mixed junction source/drain field-effect-transistor described in the present invention has the characteristics of relatively low source/drain leakage. At the same time, this field-effect-transistor has lower source/drain series resistances than that associated with P-N junction field-effect-transistors. | 05-17-2012 |
| 20120267698 | FLOATING-GATE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer. A semiconductor junction at a drain region is a P-N junction, while a semiconductor junction at a source region is a metal-semiconductor junction. | 10-25-2012 |
| 20120292733 | Mixed Schottky/P-N Junction Diode and Method of Making - The present invention relates to the field of microelectronic technology. It discloses a mixed Schottky/P-N junction diode and a method of making the same. The mixed Schottky/P-N junction diode comprises a semiconductor substrate having a bulk region and a doped region, and a conductive layer on the semiconductor substrate. The doped region has opposite doping from that of the bulk region. A P-N junction is formed between the bulk region and the doped region, a Schottky junction is formed between the conductive layer and the semiconductor substrate, and an ohmic contact is formed between the conductive layer and the doped region. The mixed Schottky/P-N junction diode of the present invention has high operating current, fast switching speed, small leakage current, high breakdown voltage, ease of fabrication and other advantages. | 11-22-2012 |
| 20130126954 | Dynamic Random Access Memory Array and Method of Making - The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array. | 05-23-2013 |
| 20140284728 | Metal Silicide Thin Film, Ultra-Shallow Junctions, Semiconductor Device and Method of Making - A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node. | 09-25-2014 |
| 20140315366 | Semiconductor Device and Method of Making - The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias. | 10-23-2014 |
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| 20130269483 | Apparatus And Method For Electromagnetic Stirring In An Electrical Arc Furnace - An apparatus for electromagnetic stirring of the steel melt in an electrical arc furnace includes two electromagnetic stirrer units, a current supply, and a control unit. The two stirrers are mounted on an outer bottom surface of the electrical arc furnace at opposites sides of a central position of the bottom surface, the current supply is operatively connected to the two electromagnetic stirrer units, and the control unit is operatively connected to the current supply to control the operation of the two electromagnetic stirrer units. | 10-17-2013 |
| 20140130636 | Method And A Control System For Controlling A Melting Process - A method of controlling a melting process in an electric arc furnace for melting a metallic material. By means of the present disclosure it is possible to minimize desired process properties such as the melting time or the total power consumption of the melting process. The method includes the steps of receiving or collecting measured data of at least one process variable, determining the current state of the process, performing an optimization of the melting process, determining a process input based on the result of the optimization, and controlling the melting process by means of the process input. A control system is also presented herein. | 05-15-2014 |
| 20140175715 | Method And Arrangement For Vortex Reduction In A Metal Making Process - A method for reducing vortex formation in molten metal when bottom tapping the molten metal from a metallurgical vessel in a metal making process. The method includes the steps of tapping the molten metal via a tapping hole in the metallurgical vessel, and providing a flow of the molten metal in the metallurgical vessel while tapping via a time-varying electromagnetic field applied to the metallurgical vessel, the flow of the molten metal being such that it constantly moves vortices in the molten metal away from a tapping hole region during the tapping to thereby prevent accumulation of the vortices for vortex formation over the tapping hole. It is also presented an arrangement for carrying out the method. | 06-26-2014 |
| 20140305261 | Method And A Control System For Controlling A Melting And Refining Process - A method and device for controlling a melting and refining process in an electric arc furnace for melting a metal, wherein the electric arc furnace includes molten and solid metal and a slag layer on the surface of the molten metal, wherein an electromagnetic stirrer is arranged for stirring the molten metal. The method includes calculating/determining masses of the molten and solid metal at a point of time, wherein the calculation is based on initial values of the molten and solid metal, an arc power supplied to the electric arc furnace, and temperatures of the molten and solid metal, determining a stirring power based on the calculated/determined masses, and supplying the determined stirring power to the electromagnetic stirrer. | 10-16-2014 |
| 20140318314 | Method For Melting Steel - A method for melting steel in an electric arc furnace (EAF). A hot heel is provided in the EAF. Metal scrap is loaded into the EAF. The metal scrap is melted in the EAF. The mass of the hot heel in relation to the mass of the metal scrap that is initially beyond the surface of the hot heel is a certain minimum. This minimum is 0.75 times the relation between the heat required to melt the metal scrap beyond the surface of the hot heel and the heat that can be taken from the hot heel without it being solidified when a theoretical heat balance calculation is applied as defined in a formula. | 10-30-2014 |
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| 20130234067 | CHROMOPHORIC POLYMER DOTS - The present invention provides, among other aspects, stabilized chromophoric nanoparticles. In certain embodiments, the chromophoric nanoparticles provided herein are rationally functionalized with a pre-determined number of functional groups. In certain embodiments, the stable chromophoric nanoparticles provided herein are modified with a low density of functional groups. In yet other embodiments, the chromophoric nanoparticles provided herein are conjugated to one or more molecules. Also provided herein are methods for making rationally functionalized chromophoric nanoparticles. | 09-12-2013 |
| 20130234068 | CHROMOPHORIC POLYMER DOTS - The present invention provides, among other aspects, stabilized chromophoric nanoparticles. In certain embodiments, the chromophoric nanoparticles provided herein are rationally functionalized with a pre-determined number of functional groups. In certain embodiments, the stable chromophoric nanoparticles provided herein are modified with a low density of functional groups. In yet other embodiments, the chromophoric nanoparticles provided herein are conjugated to one or more molecules. Also provided herein are methods for making rationally functionalized chromophoric nanoparticles. | 09-12-2013 |
| 20140350183 | CHROMOPHORIC POLYMER DOTS WITH NARROW-BAND EMISSION - Polymers, monomers, chromophoric polymer dots and related methods are provided. Highly fluorescent chromophoric polymer dots with narrow-band emissions are provided. Methods for synthesizing the chromophoric polymers, preparation methods for forming the chromophoric polymer dots, and biological applications using the unique properties of narrow-band emissions are also provided. | 11-27-2014 |
