Patent application number | Description | Published |
20150188531 | VOLTAGE REGULATOR AND RESONANT GATE DRIVER THEREOF - The present invention relates to a voltage regulator and a resonant gate driver of the voltage regulator, where the resonant gate driver is configured to drive a first power transistor and a second power transistor and includes: a first control gateway, a second control gateway, and an inductor, where: a first end of the first control gateway is connected to a first end of the second control gateway; a second end of the first control gateway is connected to a second end of the second control gateway by using the inductor; and a third end of the first control gateway is connected to the first power transistor, and a third end of the second control gateway is connected to the second power transistor. The resonant gate driver according to an embodiment of the present invention can reduce a driving period and increase a response speed. | 07-02-2015 |
20150188580 | Universal Error-Correction Circuit with Fault-Tolerant Nature, and Decoder and Triple Modular Redundancy Circuit That Apply It - A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I | 07-02-2015 |
20150195540 | System and Method for Estimating View Synthesis Distortion - System and method embodiments are provided for achieving improved View Synthesis Distortion (VSD) calculation and more accurate distortion estimation of encoded video frames. An embodiment method includes obtaining a depth map value for a video frame and determining a weighting factor for depth distortion in accordance with the depth map value. The weighting factor maps a pixel range of the depth map value to an output function having higher values for closer image objects and lower values for farther image objects. The VSD for the video frame is then calculated as a function of absolute horizontal texture gradients weighted by a depth distortion value and the weighting factor determined in accordance with the depth map value. | 07-09-2015 |
20150228768 | Tunneling Field Effect Transistor with New Structure and Preparation Method Thereof - A tunneling field effect transistor with a new structure and a preparation method thereof are provided. The tunneling field effect transistor includes an active region between a source and a drain, a gate dielectric layer, and a gate located on a side of the gate dielectric layer deviating from the source, and a tunneling region disposed between the gate dielectric layer and the source and in contact with both the gate dielectric layer and the source. The source includes at least a first area and a second area perpendicularly connected in an “L” shape. The tunneling region is in contact with at least the first area and the second area. The gate dielectric layer is in contact with at least the tunneling region and the source. | 08-13-2015 |
20150271488 | Illumination Compensation (IC) Refinement - An apparatus comprises a receiver configured to receive video views comprising a reference view and a current view, wherein the reference view comprises a reference block and the current view comprises a current block, and a processor coupled to the receiver and configured to determine neighboring reference pixels associated with the reference block, determine neighboring current pixels associated with the current block, determine a first positional pairing between the neighboring reference pixels and the neighboring current pixels, determine a second positional pairing between the neighboring reference pixels and the neighboring current pixels, and determine an optimal pairing from between the first positional pairing and the second positional pairing. | 09-24-2015 |
20150381988 | METHOD AND DEVICE FOR REDUCING A COMPUTATIONAL LOAD IN HIGH EFFICIENCY VIDEO CODING - A method for reducing a computational load in high efficiency video coding includes generating a full rate distortion calculation list of selected intra coding modes where the intra coding modes including intra prediction modes and depth modeling modes. A rate distortion cost is determined, with a segment-wise depth coding mode being disabled, for each intra prediction mode in the full rate distortion calculation list and a smallest rate distortion cost intra prediction mode is selected. A rate distortion cost for a particular intra prediction mode is calculated with the segment-wise depth coding mode enabled. After comparison, one of the particular intra prediction mode and the smallest rate distortion cost intra prediction mode having the smallest rate distortion cost is applied to a prediction unit. | 12-31-2015 |
20150382025 | METHOD AND DEVICE FOR PROVIDING DEPTH BASED BLOCK PARTITIONING IN HIGH EFFICIENCY VIDEO CODING - Depth based block partitioning in high efficiency video coding is provided by partitioning a video image block into different partitions using a binary segmentation mask. A determination is made whether to filter pixels at a boundary between the partitions. A particular pixel is not filtered in response to each adjacent pixel in vertical and horizontal planes in relation to the particular pixel having a same value. The particular pixel is filtered in response to any adjacent pixel in the vertical and horizontal planes in relation to the particular pixel having a different value than any other adjacent pixel in the vertical and horizontal planes in relation to the particular pixel. Pixels are filtered pursuant to a filtering process in response to a filtering determination. | 12-31-2015 |
20160088302 | METHOD AND APPARATUS FOR NON-UNIFORM MAPPING FOR QUANTIZATION MATRIX COEFFICIENTS BETWEEN DIFFERENT SIZES OF QUANTIZATION MATRICES IN IMAGE/VIDEO CODING - A method for non-uniform mapping for quantization matrix coefficients between different sizes of quantization matrices in image/video coding includes obtaining a first quantization matrix and identifying a second quantization matrix to be formed therefrom. The second quantization matrix is a factor of two larger than the first quantization matrix. The second quantization matrix is populated with values from the first matrix through non-uniform mapping of the first quantization matrix. Non-uniform mapping to populate the second quantization matrix includes directly mapping values of all or a portion of the first quantization matrix into a most upper left portion of the second quantization matrix and mapping up-sampling values of the first quantization matrix into a remaining portion of the second quantization matrix. A frequency position pattern may be applied to the first quantization matrix to directly map only those values within the frequency position pattern into a most upper left portion of the second quantization matrix. | 03-24-2016 |
20160105672 | System and Method for Depth Map Coding for Smooth Depth Map Area - A method for coding a coding unit that is coded with a single sample value is provided. The method selects a coding pattern from at least two predetermined coding patterns, each of which includes a plurality of boundary neighboring samples of the coding unit that have been reconstructed, and decodes the coding unit according to a value of at least one of the plurality of boundary neighboring samples of the selected coding pattern that is available. | 04-14-2016 |
Patent application number | Description | Published |
20150308018 | FABRICATION AND APPLICATION OF NANOFIBER RIBBONS AND SHEETS AND TWISTED AND NON-TWISTED NANOFIBER YARNS - The present invention is directed to nanofiber yarns, ribbons, and sheets; to methods of making said yarns, ribbons, and sheets; and to applications of said yarns, ribbons, and sheets. In some embodiments, the nanotube yarns, ribbons, and sheets comprise carbon nanotubes. Particularly, such carbon nanotube yarns of the present invention provide unique properties and property combinations such as extreme toughness, resistance to failure at knots, high electrical and thermal conductivities, high absorption of energy that occurs reversibly, up to 13% strain-to-failure compared with the few percent strain-to-failure of other fibers with similar toughness, very high resistance to creep, retention of strength even when heated in air at 450° C. for one hour, and very high radiation and IJV resistance, even when irradiated in air. Furthermore these nanotube yarns can be spun as one micron diameter yarns and plied at will to make two-fold, four-fold, and higher fold yarns. Additional embodiments provide for the spinning of nanofiber sheets having arbitrarily large widths. In still additional embodiments, the present invention is directed to applications and devices that utilize and/or comprise the nanofiber yarns, ribbons, and sheets of the present invention. | 10-29-2015 |
Patent application number | Description | Published |
20120320974 | Mode Dependent Intra Smoothing Filter Table Mapping Methods for Non-Square Prediction Units - An apparatus comprising a processor configured to determine whether to use an intra smoothing filter for a rectangular prediction unit (PU) based on a lookup table (LUT) used for square PUs, wherein a width of the rectangular PU is not equal to a height of the rectangular PU. | 12-20-2012 |
20130003832 | Simplified Bilateral Intra Smoothing Filter - A method comprising receiving a plurality of reference pixels, computing a plurality of filter coefficients based on differences between a reference pixel and neighboring reference pixels in the plurality of reference pixels, and combining the filter coefficients with the reference pixel and the neighboring reference pixels to generate a filtered value, wherein the filtered value is used for intra prediction. | 01-03-2013 |
20130188702 | Simplification of Mode Dependent Intra Smoothing - An apparatus comprising a processor configured to determine whether to apply an intra smoothing filter for a prediction unit (PU) based on a lookup table (LUT), wherein the LUT comprises data indicating the intra smoothing filter should not be applied for any PU with a block size of 8×8 pixels and associated with directional prediction mode. The disclosure also includes a method comprising generating reference samples, determining a size of a PU block, and selecting the reference samples based on PU block size, wherein filtered reference samples are not selected for PU blocks with a size of 8×8 pixels and associated with directional prediction mode. | 07-25-2013 |
20130188703 | Reference Pixel Reduction for Intra LM Prediction - A video codec comprising a processor configured to generate a prediction block for a chroma block, wherein the prediction block comprises a predicted chroma sample, wherein the predicted chroma sample is based on a filtered reconstructed luma sample located in a corresponding reconstructed luma block, a plurality of downsampled filtered reconstructed luma samples located in positions neighboring the corresponding reconstructed luma block, and a plurality of downsampled chroma samples located in positions neighboring the chroma block. | 07-25-2013 |
20140169662 | Image Retargeting Quality Assessment - A method of performing an image retargeting quality assessment comprising comparing an original image and a retargeted image in a frequency domain, wherein the retargeted image is obtained by performing a retargeting algorithm on the original image. The disclosure also includes an apparatus comprising a processor configured to perform an image retargeting quality assessment, and compare an original image and a retargeted image in a spatial domain, wherein the retargeted image is obtained by performing a retargeting algorithm on the original image, and wherein comparing the original image and the retargeted image in the spatial domain comprises comparing the original image and the retargeted image to determine an amount of shape distortion between the images. | 06-19-2014 |
20140198179 | METHOD AND APPARATUS OF DEPTH PREDICTION MODE SELECTION - There is disclosed a method, apparatus and computer program product for prediction mode selection for coding a block of a depth map. An ordered list of coding modes is obtained, wherein the ordered list of coding modes comprises a plurality of coding modes each of which is capable of being used for coding of the block. A plurality of depth modeling modes (DMMs) each of which is capable of being used for coding of the block are obtained. And whether a DMM of the plurality of DMMs is to be added into the ordered list of coding modes in accordance with a decision condition is determined. | 07-17-2014 |
20140307787 | METHOD AND APPARATUS OF DEPTH PREDICTION MODE SELECTION - There is disclosed a method, apparatus and computer program product for prediction mode selection for coding a block of a depth map. An ordered list of coding modes is obtained, wherein the ordered list of coding modes comprises a plurality of coding modes. And whether a depth modeling mode and/or a region boundary chain mode is to be added into the ordered list of coding modes in accordance with a decision condition is determined. | 10-16-2014 |
20140314271 | Systems and Methods for Pedestrian Detection in Images - System, apparatus, and method embodiments are provided for detecting the presence of a pedestrian in an image. In an embodiment, a method for determining whether a person is present in an image includes receiving a plurality of images, wherein each image comprises a plurality of pixels and determining a modified center symmetric local binary pattern (MS-LBP) for the plurality of pixels for each image, wherein the MS-LBP is calculated on a gradient magnitude map without using an interpolation process, and wherein a value for each pixel is a gradient magnitude. | 10-23-2014 |
20150049807 | Method And Apparatus Of Derivation For A Binary Partition Pattern - There is disclosed a method, device and computer-readable storage medium for decoding video data. The method includes: obtaining a reference sample array of a video block; obtaining a sum of the reference sample array; calculating a threshold by performing arithmetic right shift to the sum, a shift value of the arithmetic right shift being determined according to size information of the video block; and determining the binary partition pattern by comparing the reference sample array with the threshold. | 02-19-2015 |
20150110174 | Reference Pixel Selection and Filtering for Intra Coding of Depth Map - A video codec configured to receive a current block and a plurality of neighboring pixels, wherein the current block comprises a first partition and a second partition, select one or more reference pixels from the plurality of neighboring pixels, and predict a plurality of pixels located in the second partition based on the reference pixels. | 04-23-2015 |
Patent application number | Description | Published |
20120098098 | STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE - An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed. | 04-26-2012 |
20140061859 | STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE - An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed. | 03-06-2014 |
20140183662 | DEEP TRENCH ISOLATION WITH TANK CONTACT GROUNDING - An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit. | 07-03-2014 |
20150118861 | CZOCHRALSKI SUBSTRATES HAVING REDUCED OXYGEN DONORS - A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (≧) 10 | 04-30-2015 |
20150187934 | HIGH VOLTAGE MULTIPLE CHANNEL LDMOS - An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion. | 07-02-2015 |
20150340496 | TRANSISTOR HAVING DOUBLE ISOLATION WITH ONE FLOATING ISOLATION - A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats. | 11-26-2015 |
20160093612 | HIGH VOLTAGE MULTIPLE CHANNEL LDMOS - An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion. | 03-31-2016 |