Patent application number | Description | Published |
20090014765 | High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region. | 01-15-2009 |
20090014816 | High voltage operating field effect transistor, and bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential. | 01-15-2009 |
20100165695 | Memory Cell Array - Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less. | 07-01-2010 |
20100165696 | Memory Cell Array - Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less. | 07-01-2010 |
20100257726 | Method of Fabricating Element Including Nanogap Electrodes - Disclosed is a fabrication method of an element with nanogap electrodes including a first electrode, a second electrode provided above the first electrode, and a gap provided between the first electrode and the second electrode, the gap being in an order of nanometer to allow resistive state to be switched by applying a predetermined voltage between the first electrode and the second electrode, the method comprising: forming the first electrode; forming a spacer on an upper surface of the first electrode; forming the second electrode in contact with an upper surface of the spacer; and removing the spacer to form the gap. | 10-14-2010 |
20130119240 | PHOTOELECTRIC CONVERSION CELL AND ARRAY, READING METHOD THEREFOR, AND CIRCUIT THEREOF - In order to achieve a photovoltaic cell and an array of high sensitivity and high dynamic range, there is a need for a photovoltaic cell and an array which are combined so that an amplified photovoltaic element and a selection element are resistant to external noise, and so that the combination is resistant to effects from address selection pulse noise at array readout time. In the present invention, in order to solve the problem, a photovoltaic cell has been configured with a combination of an amplified photovoltaic element ( | 05-16-2013 |
20130155757 | Drive Method for Memory Element, and Storage Device Using Memory Element - A memory element includes an insulating substrate; a first electrode and a second electrode on the insulating substrate; and an inter-electrode gap portion that causes a change in resistance value between the first and second electrodes. Applied to the memory element from a pulse generating source is a first voltage pulse for shifting from a predetermined low-resistance state to a predetermined high-resistance state, and a second voltage pulse for shifting from the high-resistance state to the low-resistance state through a series-connected resistor, by which current flowing to the memory element after the change to a low resistance value is reduced. When shifting from the high to the low-resistance state, a voltage pulse is applied such that an electrical resistance between the pulse generating source and the memory element becomes higher than the electrical resistance shifting from the low to the high-resistance state. | 06-20-2013 |
20130170285 | Drive Method for Memory Element and Storage Device Using Memory Element - In a drive method for a memory element that includes an insulating substrate, a first electrode and a second electrode provided on the insulating substrate, and an inter-electrode gap portion provided between the first electrode and the second electrode and having a gap of the order of nanometers where a phenomenon of a change in resistance value between the first and second electrodes occurs, and that can perform a transition from a predetermined low-resistance state to a predetermined high-resistance state and a transition from the high-resistance state to the low-resistance state, a current pulse is applied to the memory element by a constant current circuit upon the transition from the high-resistance state to the low-resistance state. | 07-04-2013 |
20130234277 | SEMICONDUCTOR DEVICE AND IMAGING APPARATUS - The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region. The electrode is insulated from the first to third semiconductor regions, and current gain is variable through application of voltage to the electrode. | 09-12-2013 |
20130240716 | METHOD OF VARYING GAIN OF AMPLIFYING PHOTOELECTRIC CONVERSION DEVICE AND VARIABLE GAIN PHOTOELECTRIC CONVERSION DEVICE - Provided is a method of varying the gain of an amplifying photoelectric conversion device and a variable gain photoelectric conversion device which are capable of achieving both signal processing under low illuminance and high-current processing under high light intensity, and thereby capable of securing a wide dynamic range. An amplifying photoelectric conversion part includes a photoelectric conversion element and amplification transistors forming a Darlington circuit. The sources and the drains of field-effect transistors are connected to the bases and the emitters of the amplification transistors, respectively. The gates of the field-effect transistors each function as a gain control part. | 09-19-2013 |
20140030878 | METHOD OF MAKING LESS ELECTRIC CURRENT DEPENDENCE OF ELECTRIC CURRENT GAIN OF SEMICONDUCTOR DEVICE - An object of the present invention is to amplify the current which varies by a factor of several orders of magnitude with a constant gain without using a complicated circuit. In order to solve the problem, with a semiconductor device includes a first semiconductor region of a first conductivity, a second semiconductor region which is an opposite conductivity opposite to the first conductivity and is in contact with the first semiconductor region and a third semiconductor region which is the first conductivity and is in contact with the second semiconductor region at the second surface, a fourth semiconductor region in contact with the second semiconductor region is provided so as to be separated from the third semiconductor region and enclose the third semiconductor region and an impurity concentration of the fourth semiconductor region is larger than that of the second semiconductor region. | 01-30-2014 |
20140239158 | PHOTOELECTRIC CONVERTER, PHOTOELECTRIC CONVERTER ARRAY AND IMAGING DEVICE - A photoelectric converter includes a first pn junction comprised of at least two semiconductor regions of different conductivity types, and a first field-effect transistor including a first source connected with one of the semiconductor regions, a first drain, a first insulated gate and a same conductivity type channel as that of the one of the semiconductor regions. The first drain is supplied with a second potential at which the first pn junction becomes zero-biased or reverse-biased relative to a potential of the other of the semiconductor regions. When the first source turns to a first potential and the one of the semiconductor regions becomes zero-biased or reverse-biased relative to the other semiconductor regions, the first pn junction is controlled not to be biased by a deep forward voltage by supplying a first gate potential to the first insulated gate, even when either of the semiconductor regions is exposed to light. | 08-28-2014 |
20150075065 | METHOD FOR PROCESSING ORGANIC PHASE SUBSTANCE BY USINGHALOGEN-CONTAINING CHECICAL OR CHEMICALS AND/OR MIXTURECONTAINING OXYGEN-CONTAINING OXIDIZER OR OXIDIZERS ANDORGANIC CARBONYL ANALOGUE OR ANALOGUES, AND/ORMETHOD FOR EXTRACTING OR DEPOSITING HEAVY ELEMENT SPECIESAND/OR ORGANIC COMPONENTS OF ASPHALTENE AND/OR INORGANICSUBSTANCE FROM THE ORGANIC PHASE SUBSTANCE BY USINGHALOGEN-CONTAINING CHEMICAL OR CHEMICALS AND/OR MIXTURECONTAINING OXYGEN-CONTAINING OXIDIZER OR OXIDIZERS ANDORGANIC CARBONYL ANALOGUE OR ANALOGUES, ANDPLANT USING FOR THE METHOD, AND ORGANIC PHASE SUBSTANCE - The invention provides a processing method for upgrading an organic phase substance by removing heavy element species from the organic phase substance originating from a resource substance in mild environmental conditions, and further provides a method for collecting removed heavy element species and a method for collecting other substances. | 03-19-2015 |