Patent application number | Description | Published |
20080246062 | Semiconductor based controllable high resistance device - The field of invention is in the area of MOS integrated circuits operating with very low currents in the weak inversion region or sub threshold. The method aims at providing linear resistor with a value in the multi-mega ohm range. | 10-09-2008 |
20130083951 | LOW DISTORTION SWITCHED-CAPACITOR EVENT-DRIVEN ANALOG TO DIGITAL CONVERTER - An event-driven tracking analog to digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC non-linearity, reduces the swing and dynamic common-mode range requirement of the operational transconductance amplifier (OTA) and comparators, respectively. | 04-04-2013 |
20130313524 | AMBIPOLAR SILICON NANOWIRE FIELD EFFECT TRANSISTOR - This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts. | 11-28-2013 |
20140146132 | OMNIDIRECTIONAL SENSOR ARRAY SYSTEM - An omnidirectional sensor array system, for example a panoptic camera, comprising a plurality of sensors arranged on a support of predetermined shape to acquire data, wherein said sensors are directional and wherein each sensor is attached to a processing node which comprises integrated electronics that carries out at least a portion of the signal processing algorithms locally in order to reduce the computational load of a central hardware unit. | 05-29-2014 |
20150128823 | ROCKET OR ARTILLERY LAUNCHED SMART RECONNAISSANCE POD - A modular reconnaissance capsule or reconnaissance pod is provided that is suitable for deployment by means of an artillery launching platform, such as a conventional 40 mm grenade launcher or 155 mm cannon wherein a parachute is deployed at a pre-calculated observation altitude, the parachute being designed to yield a sufficiently slow rate of descent to permit live video capture and transmission of images as forward observation information. Alternatively, pods according to the invention may also be air dropped from an aircraft, either piloted or pilotless, thus allowing the aircraft to operate at a safe distance and yet provide close reconnaissance even under a cloud cover. Accurate information about targeting dynamics is made available to the user through commercially available products. The invention complements other reconnaissance methods and provides easy-to-use real-time visual information for a desired area of interest. | 05-14-2015 |
20150200363 | RESISTIVE SWITCHING ELEMENT AND USE THEREOF - A bipolar resistive switching device (RSM device, FIG. | 07-16-2015 |
20150319419 | Hardware-Oriented Dynamically Adaptive Disparity Estimation Algorithm and its Real-Time Hardware - A real-time stereo camera disparity estimation device comprises input means arranged to input measured data corresponding to rows of left and right images; a plurality of on-chip memories arranged to buffer the input measured data; a vertical rotator hardware module configured to align the rows of left and right images in a same column; a reconfigurable data allocation hardware module; a reconfigurable computation of metrics hardware module; and an adaptive disparity selection hardware module configured to select disparity values with the minimum matching costs. | 11-05-2015 |
20150371978 | POST-CMOS PROCESSING AND 3D INTEGRATION BASED ON DRY-FILM LITHOGRAPHY - A method for performing a post processing pattern on a diced chip having a foot-print, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern. | 12-24-2015 |