Patent application number | Description | Published |
20090001615 | SEMICONDUCTOR TEST STRUCTURES - Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds. | 01-01-2009 |
20090004879 | TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING - Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices. | 01-01-2009 |
20090004880 | MASK REUSE IN SEMICONDUCTOR PROCESSING - A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers. | 01-01-2009 |
20090087963 | METHOD FOR REDUCING PILLAR STRUCTURE DIMENSIONS OF A SEMICONDUCTOR DEVICE - A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist. | 04-02-2009 |
20090230571 | MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE - A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described. | 09-17-2009 |
20090269932 | Method for fabricating self-aligned complimentary pillar structures and wiring - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask. | 10-29-2009 |
20090321789 | Triangle two dimensional complementary patterning of pillars - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape. | 12-31-2009 |
20100012032 | Apparatus for high-rate chemical vapor deposition - An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate. | 01-21-2010 |
20100081260 | Method for forming a semiconductor film - An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate. | 04-01-2010 |
20100086875 | Method of making sub-resolution pillar structures using undercutting technique - A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask. | 04-08-2010 |
20100105210 | Method of making pillars using photoresist spacer mask - A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask. | 04-29-2010 |
20100167502 | Nanoimprint enhanced resist spacer patterning method - A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask. | 07-01-2010 |
20100167520 | Resist feature and removable spacer pitch doubling patterning method for pillar structures - A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask. | 07-01-2010 |
20100180935 | Multiple band gapped cadmium telluride photovoltaic devices and process for making the same - A heterojunction photovoltaic device for the production of electrical energy in response to the incident light includes an optically transparent substrate, a front contact formed of an transparent conductive oxide for collecting light generated charge carriers, an n-type window layer formed of cadmium sulfide or zinc sulfide, a p-type absorber structure disposed on the window layer, thereby forming a rectification junction therebetween, and a back contact comprising at least one metal layer. The p-type absorber structure has a plurality of p-type absorber layers in contiguous contact. Each absorber layer contains cadmium as a principal constituent and has a different composition and a different band gap energy. The first absorber layer is in contiguous contact with the n-type window layer. The band gap energy progressively decreases from the first absorber layer to the last absorber layer in the p-type absorber structure. | 07-22-2010 |
20100184249 | Continuous deposition process and apparatus for manufacturing cadmium telluride photovoltaic devices - A continuous deposition process and apparatus for depositing semiconductor layers containing cadmium, tellurium or sulfur as a principal constituent on transparent substrates to form photovoltaic devices as the substrates are continuously conveyed through the deposition apparatus is described. The film deposition process for a photovoltaic device having an n-type window layer and three p-type absorber layers in contiguous contact is carried out by a modular continuous deposition apparatus which has a plurality of processing stations connected in series for depositing successive layers of semiconductor films onto continuously conveying substrates. The fabrication starts by providing an optically transparent substrate coated with a transparent conductive oxide layer, onto which an n-type window layer formed of CdS or CdZnS is sputter deposited. After the window layer is deposited, a first absorber layer is deposited thereon by sputter deposition. Thereafter, a second absorber layer formed of CdTe is deposited onto the first absorber layer by a novel vapor deposition process in which the CdTe film forming vapor is generated by sublimation of a CdTe source material. After the second absorber layer is deposited, a third absorber layer formed of CdHgTe is deposited thereon by sputter deposition. The substrates are continuously conveyed through the modular continuous deposition apparatus as successive layers of semiconductor films are deposited thereon. | 07-22-2010 |
20100193916 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays. | 08-05-2010 |
20100243602 | IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK - A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A | 09-30-2010 |
20100301449 | METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY - The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed. | 12-02-2010 |
20110169126 | In-situ passivation methods to improve performance of polysilicon diode - A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated. | 07-14-2011 |
20110171815 | PATTERNING METHOD FOR HIGH DENSITY PILLAR STRUCTURES - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features. | 07-14-2011 |
20110306174 | Patterning Method for High Density Pillar Structures - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features. | 12-15-2011 |
20110310655 | Composition Of Memory Cell With Resistance-Switching Layers - A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided. | 12-22-2011 |
20120074367 | COUNTER DOPING COMPENSATION METHODS TO IMPROVE DIODE PERFORMANCE - A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided. | 03-29-2012 |
20120091418 | BIPOLAR STORAGE ELEMENTS FOR USE IN MEMORY CELLS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes (1) a bipolar storage element formed from a metal-insulator-metal (MIM) stack including (a) a first conductive layer; (b) a reversible resistivity switching (RRS) layer formed above the first conductive layer; (c) a metal/metal oxide layer stack formed above the first conductive layer; and (d) a second conductive layer formed above the RRS layer and the metal/metal oxide layer stack; and (2) a steering element coupled to the storage element. Numerous other aspects are provided. | 04-19-2012 |
20120091419 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided. | 04-19-2012 |
20120091427 | MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided. | 04-19-2012 |
20120094478 | RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES - A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask. | 04-19-2012 |
20120127779 | Re-writable Resistance-Switching Memory With Balanced Series Stack - A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area. | 05-24-2012 |
20120135603 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays. | 05-31-2012 |
20120153249 | Composition of Memory Cell With Resistance-Switching Layers - A memory cell including a first electrode, a second electrode and a first resistance-switching layer located between the first and second electrodes. The first resistance-switching layer comprises hafnium silicon oxynitride. | 06-21-2012 |
20120193756 | DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME - In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided. | 08-02-2012 |
20120276744 | Patterning Method for High Density Pillar Structures - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features. | 11-01-2012 |
20130094278 | Non-Volatile Memory Cell Containing an In-Cell Resistor - A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode. | 04-18-2013 |
20130130467 | RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES - A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided. | 05-23-2013 |
20130175492 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided. | 07-11-2013 |
20130183829 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided. | 07-18-2013 |
20130292634 | RESISTANCE-SWITCHING MEMORY CELLS HAVING REDUCED METAL MIGRATION AND LOW CURRENT OPERATION AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer between the MIM stack and the conductor. Numerous other aspects are provided. | 11-07-2013 |
20130336037 | 3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF - A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. | 12-19-2013 |
20140254231 | 3D Non-Volatile Memory Having Low-Current Cells and Methods - A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described. | 09-11-2014 |
20140284538 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided. | 09-25-2014 |
20140284697 | VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND LANDING PAD - A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. | 09-25-2014 |
20140346433 | MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided. | 11-27-2014 |
20140374688 | High Capacity Select Switches for Three-Dimensional Structures - A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line. | 12-25-2014 |