Patent application number | Description | Published |
20100314758 | THROUGH-SILICON VIA STRUCTURE AND A PROCESS FOR FORMING THE SAME - A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer. | 12-16-2010 |
20110108986 | THROUGH-SILICON VIA STRUCTURE AND A PROCESS FOR FORMING THE SAME - A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof. | 05-12-2011 |
20110193221 | 3DIC Architecture with Interposer for Bonding Dies - A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure. | 08-11-2011 |
20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
20110285005 | PACKAGE SYSTEMS HAVING INTERPOSERS - A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. | 11-24-2011 |
20120007154 | TSV Formation Processes Using TSV-Last Approach - A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad. | 01-12-2012 |
20120068218 | THERMALLY EFFICIENT PACKAGING FOR A PHOTONIC DEVICE - The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire. | 03-22-2012 |
20120083116 | Cost-Effective TSV Formation - A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. | 04-05-2012 |
20130093042 | TSV Formation Processes Using TSV-Last Approach - A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad. | 04-18-2013 |
20130140690 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 06-06-2013 |
20130171772 | THROUGH-SILICON VIA STRUCTURE FORMATION PROCESS - In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening. | 07-04-2013 |
20130285244 | Through Silicon Via with Embedded Barrier Pad - A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. | 10-31-2013 |
20130302979 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS - A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate. | 11-14-2013 |
20140077374 | Through Via Structure and Method - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. | 03-20-2014 |
20140287581 | Through Silicon Via with Embedded Barrier Pad - A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. | 09-25-2014 |
20140342547 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 11-20-2014 |
20150035159 | SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME - A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. | 02-05-2015 |
20150054174 | Interconnection Structure with Confinement Layer - An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad. | 02-26-2015 |
20150061147 | Device with Through-Substrate Via Structure and Method for Forming the Same - A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure. | 03-05-2015 |
20150137360 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 05-21-2015 |
20150147834 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 05-28-2015 |
20150206823 | Robust Through-Silicon-Via Structure - Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features. | 07-23-2015 |
20150206846 | Interconnect Structure and Method of Forming Same - An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer. | 07-23-2015 |
20150249049 | Through-Substrate via Formation with Improved Topography Control - A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad. | 09-03-2015 |
20150348872 | Dummy Structure for Chip-on-Wafer-on-Substrate - Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines. | 12-03-2015 |
20150357263 | Through Via Structure - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. | 12-10-2015 |
20160035609 | Wafer Cassette with Electrostatic Carrier Charging Scheme - A wafer cassette includes a main body having space to hold at least one wafer assembly. Each of the at least one wafer assembly includes a wafer and an electrostatic carrier attached to the wafer. An electrical contact structure inside the main body is arranged to contact an electrical pad of the electrostatic carrier. | 02-04-2016 |
Patent application number | Description | Published |
20100130034 | Flexible printed circuit board connector - A flexible printed circuit board connector adapted for receiving a flexible printed circuit board has an insulating housing including two blocking walls, each defines a lateral side having a buckling cavity at a front thereof and a first and second locating cavities at a rear thereof. The buckling cavity includes a first buckling cavity and a second buckling cavity extending frontward from the first buckling cavity. The second locating cavity is located in front of and spaced from the first locating cavity. A cover defines two lateral plates respectively secured to the lateral sides, each has a locating portion and a buckling portion respectively protruded inwards from an inner side thereof. The locating portion is capable of being pivotally mounted in the first locating cavity, and then the locating portion and the buckling portion can be moved frontward to the second locating cavity and the second buckling cavity, respectively. | 05-27-2010 |
20100130068 | Board-to-board connector assembly - A board-to-board connector assembly includes a receptacle connector having a plurality of first terminals, and a plug connector having a plurality of second terminals. Each of the first terminals has a first contact portion and a second contact portion and each of the second terminals has a first contact arm and a second contact arm. When the plug connector is mated with the receptacle connector, the first contact portion and the second contact portion of the first terminal electrically contact the first contact arm and the second contact arm of the corresponding second terminal respectively to make the first terminal and the corresponding second terminal electrically interconnected steadily. | 05-27-2010 |
20100136821 | Connector terminal and method for making the same - A connector terminal mounted in a flexible printed circuit board connector for electrically connecting with the flexible printed circuit board includes a fixing portion of strip shape, a soldering portion connecting with one end of the fixing portion and a contacting portion extending upwards from the other end of the fixing portion to show an arc shape. The contacting portion has a retaining portion protruding from a peak thereof. The retaining portion includes a smooth contacting surface for contacting the flexible printed circuit board and an end surface defined at one end thereof. The contacting surface and the end surface define a sharp junction therebetween. A peak of the sharp junction is capable of interfering with the flexible printed circuit board. | 06-03-2010 |
20100136838 | BATTERY CONNECTOR - A battery connector adapted for being electrically connected with a printed circuit board includes an insulating housing defining a plurality of terminal passageways, a plurality of fixing members fastened in the insulating housing and stretching beyond a top surface of the insulating housing for being soldered to the printed circuit board, and a plurality of electrical terminals disposed in the corresponding terminal passageways and each having a fixing board, a first contact portion stretching out of a bottom surface of the insulating housing and a substantially lying-V shaped second elastic portion extended from a top of the fixing board. A free end of the second elastic portion stretches out of the top surface of the insulating housing and is arched upward to form a second contact portion capable of elastically abutting against the printed circuit board. | 06-03-2010 |
20100167585 | ELECTRICAL CONNECTOR WITH IMPROVED BUCKLING TAB - An electrical connector has an insulating housing defining a recess. A receiving plate extends frontward from a rear surface of the recess and spaced apart from a bottom surface thereof. A shell coupled with the insulating housing to form an insertion space where the receiving plate is located has a connecting plate located between the receiving plate and the bottom surface of the recess. A portion of the connecting plate is extended and curved upwards and then curved downwards and upwards sequentially to form a substantial split ring-shaped resilient element. The resilient element comprises an upper resistive portion located adjacent to the receiving plate and a lower resistive portion located adjacent to the bottom surface of the recess. A free end of the lower resistive portion extends obliquely upwardly to form a connecting portion. A distal end of the connecting portion forms a propping portion located above the connecting plate. | 07-01-2010 |
20100291776 | Board-To-Board Connector Assembly - A board-to-board connector assembly includes a receptacle connector having a plurality of first terminals, and a plug connector having a plurality of second terminals. Each of the first terminals has an elastic arm oppositely defining two first contact portions, and a first contact arm spaced away from the elastic arm. Each of the second terminals has a second contact arm defining two opposite contact means, and a third contact arm defining a second contact portion towards the second contact arm. When the plug connector is mated with the receptacle connector, the elastic arm of the first terminal is disposed between the second and third contact arms of the corresponding second terminal to make the two first contact portions electrically contact one of the two contact means and the second contact portion respectively, and the first contact arm electrically abuts against the other contact means. | 11-18-2010 |
Patent application number | Description | Published |
20130178112 | Connection Interface and Cable - The invention discloses a connection interface. The connection interface includes a first set of pins, including a plurality of pins corresponding to Universal Serial Bus (USB) 3.0 specifications; and a second set of pins, including a plurality of pins corresponding to USB 2.0 specifications; wherein the first set of pins and the second set of pins are arranged side-by-side with each other, and the second set of pins are arranged according to a front panel header definition of the USB 2.0 specifications. | 07-11-2013 |
20140342609 | INTERFACE CARD APPARATUS - An interface card apparatus is provided. The interface card includes a transmission interface, an interface converter, a system on chip, a first connector, a bus switch, a network connector, and a power switch. The transmission interface includes a data channel, a power pin, a network channel, a switch pin, a power enabling pin, and a sharing pin. The system on chip, controlled by the sharing pin, performs a file sharing program. The bus switch, controlled by the switch pin, couples the connector to the channel or the interface converter. The network connector is coupled the system on chip and the network channel, and the power switch, controlled by the power enabling pin, couples the power pin to the system on chip. | 11-20-2014 |
20140344561 | COMPUTER - A computer host comprises a first system control chip and a control unit. The file sharing circuit comprises a second system control chip, a bus switch, a power switch and a sharing button. The bus switch controlled by the control unit couples a storage apparatus to the first or the second system control chip. The power switch is controlled by the control unit to supply power to the storage apparatus, the second system control chip and the bus switch. The sharing button enables or disables a file sharing procedure and electrically connects to the first system control chip and the second system control chip. When the file sharing procedure is enabled, the control unit controls the bus switch to switch to a first state, such that the second system control chip accesses the storage apparatus. | 11-20-2014 |
20140344607 | FILE SHARING CIRCUIT AND COMPUTER USING THE SAME - File sharing circuit and computer using the same are provided. The computer includes a computer host and a file sharing circuit. The computer host includes a first storage device, a first system control chip, a control unit, and a power integrated circuit. The file sharing circuit includes a second system control chip and a first bus switch. When the second system control chip performs a file sharing procedure, the power integrated circuit powers the first storage device, the second system control chip, and the first bus switch, and the control unit switches the first bus switch to a first state so that the second system control chip accesses the first storage device. When the second system control chip does not perform the file sharing procedure, the control unit switches the first bus switch to a second state so that the first system control chip accesses the first storage device. | 11-20-2014 |