Yuichi Harada
Yuichi Harada, Aichi JP
Patent application number | Description | Published |
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20090261638 | VEHICLE SEAT WITH MONITOR - According to one embodiment of the invention, there is provided a vehicle seat with a monitor, including: a seat back; a headrest including: a head receiving portion receiving a back of a head of a vehicle occupant; a hollow recess being formed on a reverse side of the head receiving portion, the headrest being disposed such that the monitor unit at least partly enters the hollow recess; a stay mounting to the seatback, the stay being detachably attached to the headrest; and an actuating mechanism capable of moving back and forth the head receiving portion relatively with respect to the seatback, the actuating mechanism being provided at a connecting portion between the stay of the headrest and the head receiving portion; and a monitor unit including the monitor, the monitor unit being installed above the seatback and in a rear of a headrest. | 10-22-2009 |
Yuichi Harada, Matsumoto City JP
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20090085117 | LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE THEREOF - A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning. | 04-02-2009 |
20120299108 | SEMICONDUCTOR DEVICE - By connecting a protection diode ( | 11-29-2012 |
Yuichi Harada, Tsukuba JP
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20140008666 | SILICON CARBIDE VERTICAL FIELD EFFECT TRANSISTOR - A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer. | 01-09-2014 |
Yuichi Harada, Matsumoto-Shi JP
Patent application number | Description | Published |
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20150053998 | SEMICONDUCTOR DEVICE - A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode. | 02-26-2015 |
20150069415 | SEMICONDUCTOR DEVICE - An n-type SiC layer is formed on a front face of an n | 03-12-2015 |
20150076519 | VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD OF VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS - A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer. | 03-19-2015 |
20150108501 | SEMICONDUCTOR DEVICE - In an active region, p | 04-23-2015 |