Patent application number | Description | Published |
20090029547 | NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION - A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps. | 01-29-2009 |
20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 05-21-2009 |
20100091163 | Image Sensor Having Enhanced Backside Illumination Quantum Efficiency - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching. | 04-15-2010 |
20110081766 | METHOD FOR DOPING A SELECTED PORTION OF A DEVICE - A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness. | 04-07-2011 |
20140061924 | Interconnect Structure and Method - An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line. | 03-06-2014 |
20150041874 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 02-12-2015 |
Patent application number | Description | Published |
20080217775 | Method of forming contact plugs for eliminating tungsten seam issue - A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole. | 09-11-2008 |
20080318378 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 12-25-2008 |
20090051034 | Semiconductor device and method for the same - A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer. | 02-26-2009 |
20120217611 | INTEGRATED CIRCUITS INCLUDING CONDUCTIVE STRUCTURES THROUGH A SUBSTRATE AND METHODS OF MAKING THE SAME - An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap. | 08-30-2012 |
20120280358 | INTEGRATED CIRCUITS INCLUDING METAL-INSULATOR-METAL CAPACITORS AND METHODS OF FORMING THE SAME - An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer. | 11-08-2012 |
20130093098 | THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME - The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill. | 04-18-2013 |
20130320493 | CAPACITOR FOR INTERPOSERS AND METHODS OF MANUFACTURE THEREOF - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers. | 12-05-2013 |
20140327151 | THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME - A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section. | 11-06-2014 |
20150037960 | METHOD OF MANUFACTURING A CAPACITOR - A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor. | 02-05-2015 |