Patent application number | Description | Published |
20080230852 | Fabrication of FinFETs with multiple fin heights - A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses. | 09-25-2008 |
20080265321 | Fin Field-Effect Transistors - A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used. | 10-30-2008 |
20080265338 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 10-30-2008 |
20090035909 | METHOD OF FABRICATION OF A FINFET ELEMENT - The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type. | 02-05-2009 |
20090096002 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 04-16-2009 |
20090250769 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 10-08-2009 |
20090253266 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 10-08-2009 |
20100144121 | Germanium FinFETs Having Dielectric Punch-Through Stoppers - A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin. | 06-10-2010 |
20100184281 | METHOD FOR TREATING LAYERS OF A GATE STACK - A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof. | 07-22-2010 |
20100258870 | FINFETS AND METHODS FOR FORMING THE SAME - A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap. | 10-14-2010 |
20110037129 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 02-17-2011 |
20110147810 | METHOD OF FABRICATING STRAINED STRUCTURE IN SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate. | 06-23-2011 |
20110171805 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 07-14-2011 |
20120025313 | Germanium FinFETs Having Dielectric Punch-Through Stoppers - A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin. | 02-02-2012 |
20120211807 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 08-23-2012 |
20130009245 | Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof - Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric. | 01-10-2013 |
20130143406 | TECHNIQUES PROVIDING PHOTORESIST REMOVAL - A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone. | 06-06-2013 |
20140070318 | Reducing Resistance in Source and Drain Regions of FinFETs - A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer. | 03-13-2014 |