Patent application number | Description | Published |
20080253722 | FIBER OPTIC TELECOMMUNICATIONS CABLE ASSEMBLY - The present disclosure relates to a fiber optic telecommunications cable assembly including a main fiber optic cable and a tether cable that branches from the main fiber optic cable at a breakout location. The fiber optic telecommunications cable assembly also includes a breakout block mounted to the main fiber optic cable at the breakout location, and an over-mold that covers the breakout block and at least a portion of the main fiber optic cable. The breakout block defines a straight-through channel in which the main fiber optic cable is received and a breakout channel that branches out from the straight-through channel. The breakout block includes seams with overlap configurations that prevent the over-mold from entering the breakout block through the seams. The breakout block also includes barrier dams for preventing bonding material from entering the breakout channel. | 10-16-2008 |
20080253729 | Fiber optic cable breakout configuration with tensile reinforcement - The present disclosure relates to a fiber optic telecommunications cable assembly including a main fiber optic cable and a tether cable that branches from the main fiber optic cable at a breakout location. The breakout location includes a breakout block mounted to the main fiber optic cable, a tether retention block mounted to the main fiber optic cable, and a sleeve positioned outside the main fiber optic cable that extends from the breakout block to the tether retention block. An optical fiber structure extends from the main fiber optic cable, through the breakout block, through the sleeve and through the tether retention block to the tether cable. The fiber optic telecommunications cable assembly also includes a tensile reinforcing structure that extends from the breakout block to the retention block for preventing a spacing between the breakout block and the retention block from exceeding a predetermined amount. The tensile reinforcing structure is positioned outside the main fiber optic cable and has portions anchored to the breakout block and the retention block. The fiber optic telecommunications cable assembly further includes an over-mold that covers the breakout block, the sleeve, the retention block, the tensile reinforcing structure and at least a portion of the main fiber optic cable. | 10-16-2008 |
20090022459 | Fiber optic cable breakout configuration with retention block - A telecommunications cable includes a distribution cable, a tether that branches from the distribution cable, and a tether retention block affixed to the distribution cable. The tether retention block includes a first portion and a second portion that is configured to cooperate with the first portion to secure a tether buffer tube and a strength member of the tether. Each of the first and second portions defines at least a first half-channel configured to cooperate with the first half-channel of the other portion to receive the strength member of the tether. | 01-22-2009 |
20090275267 | Method of manufacturing ferrule assemblies - A method of manufacturing a ferrule assembly. The method including first and second polishing operations. The first polishing operation including polishing only the end face of a ferrule of an assembly. The second polishing operation including polishing only the optical fiber of the assembly. | 11-05-2009 |
20100046905 | Splitter Modules for Fiber Distribution Hubs - A splitter module for a fiber distribution hub includes a main body with a first aperture configured to receive an input fiber entering the splitter module, and a second aperture configured for a plurality of distribution fibers exiting the splitter module. The splitter module also includes a fin configured to be received in a slot of a splitter tray of a fiber distribution hub, and a pin configured to engage a hole in the splitter tray. The fin is received in the slot, and the pin is received in the hole of the fiber distribution hub to couple the splitter module to the fiber distribution module. | 02-25-2010 |
20110092138 | Method of manufacturing ferrule assemblies - A method of manufacturing a ferrule assembly. The method including first and second polishing operations. The first polishing operation including polishing only the end face of a ferrule of an assembly. The second polishing operation including polishing only the optical fiber of the assembly. | 04-21-2011 |
Patent application number | Description | Published |
20090279354 | Stacked Magnetic Devices - Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level. | 11-12-2009 |
20100002486 | MAGNETIC SHIFT REGISTER MEMORY DEVICE - In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains. | 01-07-2010 |
20120182781 | MAGNETIC SHIFT REGISTER MEMORY DEVICE - In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains. | 07-19-2012 |
20130094282 | MULTI-BIT SPIN-MOMENTUM-TRANSFER MAGNETORESISTENCE RANDOM ACCESS MEMORY WITH SINGLE MAGNETIC-TUNNEL-JUNCTION STACK - A magneto resistive random access memory system includes a first magnetic-tunnel-junction device coupled to a first bit-line, a second magnetic-tunnel-junction device coupled to a second bit-line, a selection transistor coupled to the first and second bit-lines and a word-line coupled to the selection transistor. | 04-18-2013 |
20130126830 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20130130446 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20140217481 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 08-07-2014 |
20140312412 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer. | 10-23-2014 |
20140312413 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer. | 10-23-2014 |
20140332860 | STACKED CARBON-BASED FETS - Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions. | 11-13-2014 |
20140332862 | STACKED CARBON-BASED FETS - Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions. | 11-13-2014 |
20150187764 | STACKED CARBON-BASED FETS - A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions. | 07-02-2015 |
20150187897 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 07-02-2015 |
20150228753 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer. | 08-13-2015 |
Patent application number | Description | Published |
20150249209 | SELF-ALIGNED TOP CONTACT FOR MRAM FABRICATION - Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ. | 09-03-2015 |
20150280112 | MAGNETIC TUNNEL JUNCTION AND METHOD FOR FABRICATING A MAGNETIC TUNNEL JUNCTION - An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode. | 10-01-2015 |
20150287910 | REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH - A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask. | 10-08-2015 |
20150311429 | MAGNETIC TUNNEL JUNCTION AND METHOD FOR FABRICATING A MAGNETIC TUNNEL JUNCTION - An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode. | 10-29-2015 |
20150340593 | ETCH-RESISTANT PROTECTIVE COATING FOR A MAGNETIC TUNNEL JUNCTION DEVICE - A method of forming a magnetic tunnel junction (MTJ) device includes forming a spacer on an exposed side portion of the MTJ device. The method further includes forming an etch-resistant protective coating associated with the MTJ device. The etch-resistant protective coating provides greater etch resistance than the spacer. | 11-26-2015 |