Patent application number | Description | Published |
20130134425 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer. | 05-30-2013 |
20130161625 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer. | 06-27-2013 |
20140127844 | MANUFACTURING METHOD OF ARRAY SUBSTRATE - A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer. | 05-08-2014 |
20150123128 | ARRAY SUBSTRATE - The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT. | 05-07-2015 |
20150126006 | MANUFACTURING METHOD OF ARRAY SUBSTRATE - A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer. | 05-07-2015 |
Patent application number | Description | Published |
20090269874 | METHOD FOR FABRICATING FLEXIBLE PIXEL ARRAY SUBSTRATE - In a method for fabricating a flexible pixel array substrate, first, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate. | 10-29-2009 |
20100080977 | STRUCTURE OF THERMAL RESISTIVE LAYER AND THE METHOD OF FORMING THE SAME - The prevent invention discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is easy to carry out. | 04-01-2010 |
20110297550 | METHOD OF FORMING THE STRUCTURE OF THERMAL RESISTIVE LAYER - The prevent disclosure discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is possible. | 12-08-2011 |
Patent application number | Description | Published |
20140193446 | BIODEGRADABLE HIGH-EFFICIENCY DENGUE VACCINE, METHOD FOR MAKING THE SAME, AND PHARMACEUTICAL COMPOSITION COMPRISING THE SAME - The present invention is related to a biodegradable high-efficiency dengue vaccine, a method for making the same, and a pharmaceutical composition comprising the same. The biodegradable high-efficiency dengue vaccine comprises a biodegradable nanocomplex with electric properties holding a dengue viral protein inside. An organism has antibody responses after vaccination with the biodegradable nanocomplex twice. Accordingly, in comparison with the Alum adjuvant and Ribi adjuvant used in the traditional dengue vaccine of the prior art, the vaccination times in the present invention is decreased to further reduce the vaccination cost, so the biodegradable high-efficiency dengue vaccine is good for being a commercial vaccine. | 07-10-2014 |
20140193505 | BIODEGRADABLE CARRIER WITH ADJUSTABLE ZETA POTENTIALS AND PARTICLE SIZES, METHOD FOR MAKING THE SAME, AND PHARMACEUTICAL COMPOSITION COMPRISING THE SAME - The present invention is related to a biodegradable carrier with adjustable zeta potentials and particle sizes, a method for making the same, and a pharmaceutical composition comprising the same. In such a method, a first solution comprising a first biodegradable macromolecule is prepared, and a second solution comprising a second biodegradable macromolecule is also prepared according to a desired zeta potential of a biodegradable carrier and further added into the first solution to form a mixture solution. The biodegradable carrier with the desired zeta potentials is formed by the attraction force between the different electric properties. Then, the mole number of the first biodegradable macromolecule and the second biodegradable macromolecule in the mixture solution are proportionally adjusted according to a desired particle size of the biodegradable carrier. Therefore, the zeta potential and the particle size of the biodegradable carrier are adjustable artificially. | 07-10-2014 |
20140246751 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer. | 09-04-2014 |
20150132918 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer. | 05-14-2015 |
Patent application number | Description | Published |
20130078755 | METHOD OF MANUFACTURING THIN FILM SOLAR CELLS - A method for manufacturing thin film solar cells, includes forming a light permeable first electrode layer in the back light surface of a glass substrate, and formed in the first electrode layer a plurality of first openings for exposing a part of the back light surface therefrom; forming a photoelectric conversion layer on the first electrode layer and the exposed back light surface, and forming a plurality of second openings in the photoelectric conversion layer for exposing a part of the first electrode layer therefrom; and forming a glistening second electrode layer having a plurality of third openings formed therein, wherein the second electrode layer comprises a conductive colloid comprised of non-diffractive fillings and polymeric base material. | 03-28-2013 |
20130276871 | P-I-N MICROCRYSTALLINE SILICON STRUCTURE OF THIN-FILM SOLAR CELLS AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a P-I-N microcrystalline silicon structure for thin-film solar cells, includes the steps of: (a) forming a P-type layer; (b) forming an I-type layer including a plurality of sub-layers successively stacked on the P-type layer using gas mixtures including fluoride and hydride that have different gas ratios, respectively; and (c) forming an N-type layer on the I-type layer. First, second, and third I-type sub-layers may be formed on the P-type layer using gas mixtures including fluoride and hydride at a first, second, and third gas ratios, respectively. Then, advantageously, the third gas ratio may be larger than the second gas ratio and the second gas ratio may be larger than the first gas ratio, and the first gas ratio may be 8%, the second gas ratio may range between 15% and 35%, and the third gas ratio may range between 35% and 50%. | 10-24-2013 |
20150129025 | HIT SOLAR CELL - A HIT solar cell is provided, including a p-type crystalline silicon substrate having a light-receiving surface, a first intrinsic amorphous silicon thin-film layer formed on the light-receiving surface of the p-type crystalline silicon substrate, an n-type amorphous oxide layer formed on the first intrinsic amorphous silicon thin-film layer, and a first transparent conductive layer formed on the n-type amorphous oxide layer. In the HIT solar cell, the n-type amorphous oxide layer can be directly formed, without forming the first intrinsic amorphous silicon thin-film layer, and the n-type amorphous oxide layer can be divided into an n | 05-14-2015 |
Patent application number | Description | Published |
20110263092 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present disclosure discloses an exemplary method for fabricating a semiconductor device comprises selectively growing a material on a top surface of a substrate; selectively growing a protection layer on the material; and removing a portion of the protection layer in an etching gas. | 10-27-2011 |
20120168821 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate. | 07-05-2012 |
20130084682 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity. | 04-04-2013 |
20130122675 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle. | 05-16-2013 |
20130244389 | STRAINED SEMICONDUCTOR DEVICE WITH FACETS - A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate. The method further includes selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH | 09-19-2013 |
20140134818 | METHOD FOR FORMING EPITAXIAL FEATURE - The present disclosure provides an integrated circuit device and method for manufacturing the integrated circuit device. The disclosed method provides substantially defect free epitaxial features. An exemplary method includes forming a gate structure over the substrate; forming recesses in the substrate such that the gate structure interposes the recesses; and forming source/drain epitaxial features in the recesses. Forming the source/drain epitaxial features includes performing a selective epitaxial growth process to form an epitaxial layer in the recesses, and performing a selective etch back process to remove a dislocation area from the epitaxial layer. | 05-15-2014 |
20140367768 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution. | 12-18-2014 |
Patent application number | Description | Published |
20140264493 | Semiconductor Device and Fabricating the Same - A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate. | 09-18-2014 |
20150041761 | Backside Illuminated Photo-Sensitive Device with Gradated Buffer Layer - A method for forming a backside illuminated photo-sensitive device includes forming a gradated sacrificial buffer layer onto a sacrificial substrate, forming a uniform layer onto the gradated sacrificial buffer layer, forming a second gradated buffer layer onto the uniform layer, forming a silicon layer onto the second gradated buffer layer, bonding a device layer to the silicon layer, and removing the gradated sacrificial buffer layer and the sacrificial substrate. | 02-12-2015 |
20150108430 | TRANSISTOR CHANNEL - A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material. | 04-23-2015 |
20150115397 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer. | 04-30-2015 |
20150243763 | PERFORMANCE BOOST BY SILICON EPITAXY - The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance. | 08-27-2015 |
20150263123 | COMMON SOURCE OXIDE FORMATION BY IN-SITU STEAM OXIDATION FOR EMBEDDED FLASH - The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer. | 09-17-2015 |
20150279894 | CMOS Image Sensor with Epitaxial Passivation Layer - The present disclosure provides a complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device. In accordance with some embodiments, the device includes a semiconductor region having a front surface and a back surface; a light-sensing region extending from the front surface towards the back surface within the semiconductor region; a gate stack formed over the semiconductor region; and at least one epitaxial passivation layer disposed at least one of over and below the light-sensing region. In some embodiments, the at least one epitaxial passivation layer includes a p-type doped silicon (Si) layer. | 10-01-2015 |
20150303265 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer. | 10-22-2015 |
20150349160 | Backside Illuminated Photo-Sensitive Device With Gradated Buffer Layer - A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer. | 12-03-2015 |
20160111511 | TRANSISTOR WITH PERFORMANCE BOOST BY EPITAXIAL LAYER - The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance. | 04-21-2016 |
Patent application number | Description | Published |
20130230612 | GLASS REPAIRER - A glass repairer of the present invention includes a support base for fixation, a fluid-receiving tube, a pressing rod, and a rubber head for injecting repairing fluid. The fluid-receiving tube is disposed on the support base. The rubber head is fixed to an end of the pressing rod and is able to squeeze the repairing fluid in the fluid-receiving tube outward. Thereby, replenishing repairing fluid and cleaning become easier. Also, the present invention is able to be utilized repeatedly. | 09-05-2013 |
20140117547 | BARRIER LAYER FOR COPPER INTERCONNECT - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer. | 05-01-2014 |
20140191402 | Barrier Layer for Copper Interconnect - A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 07-10-2014 |
20140264872 | Metal Capping Layer for Interconnect Applications - An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer. | 09-18-2014 |
20140332962 | Device and Method for Reducing Contact Resistance of a Metal - A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N | 11-13-2014 |
20150044867 | Barrier Layer for Copper Interconnect - A device and a method of forming the device is provided. The device includes a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 02-12-2015 |
20150235956 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer. | 08-20-2015 |
20150255396 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material. | 09-10-2015 |
20150262870 | Barrier Structure for Copper Interconnect - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer. | 09-17-2015 |
20150262938 | Barrier Structure for Copper Interconnect - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer. | 09-17-2015 |
20150311150 | Metal Contact Structure and Method of Forming the Same - A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer. | 10-29-2015 |
20150318243 | Composite Contact Plug Structure and Method of Making Same - An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium. | 11-05-2015 |
20150325484 | METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER - Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine. | 11-12-2015 |
20150369446 | LIGHTING DEVICE FOR A SHEET METAL AND SYSTEM HAVING THE SAME - A lighting device for a sheet metal is provided, for emitting lights on a sheet metal. The lighting device includes: a bottom plate; a wireless remote module, including a signal receiver for receiving a wireless control signal; a plurality of lighting modules, for emitting a plurality of light colors; a cover body, covering the lighting modules and including a light translucent portion and a light opaque portion. The wireless remote module controls the lighting modules to emit light. The light from the lighting modules goes through the light translucent portion and projects a projection boundary defined by a common boundary constructed by the light translucent portion and the light opaque portion on the sheet metal. A lighting system for a sheet metal is also provided, including the lighting device described above and a support device. The lighting device is adjustably assembled with the support device. | 12-24-2015 |
20160005824 | CONTACT STRUCTURES AND METHODS OF FORMING THE SAME - Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region. | 01-07-2016 |
20160043035 | Contact Structure and Method of Forming - Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening. | 02-11-2016 |
20160049362 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer. | 02-18-2016 |
20160111327 | Device and Method for Reducing Contact Resistance of a Metal - A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer. | 04-21-2016 |
Patent application number | Description | Published |
20130109233 | USB FEMALE CONNECTOR | 05-02-2013 |
20130130521 | USB FEMALE CONNECTOR - The USB female connector contains an insulating base and a shielding casing enclosing the insulating base. On the insulating base, there is mainly a ground terminal having a flat ground contact section at an end on the insulating base. From the ground contact section, the ground terminal is extended away from the insulating base and forked into a first ground extension section, a second ground extension section, and a third ground extension section. Through the forked first, second, and third ground extension sections, the high-frequency crosstalk problem is effectively resolved. | 05-23-2013 |
20130217272 | USB 3.0 TWO-WAY SOCKET JACK CONNECTOR STRUCTURE - A USB 3.0 socket jack connector structure allows a USB plug connector to conduct working when it is plugged in the jack connector of the present invention positively or oppositely through a two-war sharing grounding transmission conductor, and a first signal transmission conductor, second signal transmission conductor, first differential signal transmission conductor, second differential signal transmission conductor, third grounding transmission conductor, third differential signal transmission conductor, fourth differential signal transmission conductor, first power supply transmission conductor, third signal transmission conductor, fourth signal transmission conductor, second power supply transmission conductor, fourth grounding transmission conductor, fifth differential signal transmission conductor, sixth differential signal transmission conductor, seventh differential signal transmission conductor and eighth differential signal transmission conductor. | 08-22-2013 |
20140080332 | USB PLUG CONNECTOR STRUCTURE - A USB plug connector structure can use the same set of terminals to apply on different USB connector patterns, such as plate edge connector or wire edge connector, through the design of various soldering portions and base portions being positioned on the same plane. Furthermore, the common mode signals generated from first and second differential signal transmission conductor sets can be restrained by means of first and second grounding base portions of a grounding transmission conductor surrounding first and second differential signal transmission conduct sets. In addition, crosstalk interference generated from the first and second differential signal transmission conductor sets to a signal transmission conductor set can be similarly isolated through the first and second grounding base portions. Furthermore, a bended angle of each bended portion ranges from 120 to 150 degrees, thereby guide scattered radio frequency interference. | 03-20-2014 |
20140127942 | APPLICATION STRUCTURE FOR ELECTRIC WAVE EFFECT OF TRANSMISSION CONDUCTOR - An application structure for an electric wave effect of transmission conductor solves a high frequency crosswalk problem through the following structures. The applicature structure includes at least one transmission conductor, and the application structure includes a first differential signal transmission conductor set, first signal transmission conductor set, second differential signal transmission conductor set, first ground transmission conductor, third differential signal transmission conductor set, second signal transmission conductor set, fourth differential signal transmission conductor set, first power source transmission conductor, second power transmission conductor and second ground transmission conductor. Whereby, the suppression of common mode signals, and the guiding-to-scatter suppression of radio wave interference (RFI), electromagnetic wave interference (EMI), crosstalk and electrostatic discharge (ESD) can be achieved between each two differential signal conductors through the first and second ground transmission conductors depending on the structure components mentioned above. | 05-08-2014 |
20150061394 | BACKUP POWER SUPPLYING DEVICE HAVING PROGRAMMABLE CURRENT-BALANCING CONTROL - A backup power supplying device having programmable current-balancing control includes at least two power modules connected in parallel. The power module includes a power converter, a current sensing component, a potential tuner, a microprocessor, a current-balancing control circuit and an output voltage controller. The current sensing component senses an output current of the power converter to generate a current sensing signal. The microprocessor controls the potential tuner to generate a tuning signal, and receives a mode signal to control the power module to operate in a power supply or sleep mode. The current-balancing control circuit receives the current sensing signal, the tuning signal and the mode signal. When the power module operates in the sleep mode, an output voltage of the power converter is a sleep voltage; a voltage level of the sleep voltage is lower than a voltage level of a supply voltage by a predetermined voltage value. | 03-05-2015 |
20150087185 | ACCESSORY CONNECTOR - An accessory connector generally includes a plurality of metal conductive terminals, which is arranged not to contact each other so as to form individual pins; a first insertion port, which is formed at one end of the accessory connector; and a second insertion port, which is formed at an opposite end of the accessory connector and is in electrical connection with the first insertion port. The first and second insertion ports can be respectively in a plug form or a socket form. When it is desired to make a conversion into a different type of insertion port, the conversion can be achieved through electrical connection of the first insertion port to the second insertion port via the metal conductive terminals so as to achieve the purpose of conversion of connector. | 03-26-2015 |
20150091380 | POWER CONVERSION DEVICE WITH MULTIPLE INTERFACES - A power conversion device with multiple interfaces generally includes at least one multiple-in-one connector, at least one circuit board, and a power supply module. The multiple-in-one connector and the power supply module are electrically connected to the circuit board. The power supply module satisfies the standard of an electric main socket or an automobile socket. Further, the multiple-in-one connector can be of a multiple-in-one connector that has a single plugging port and includes a USB interface combined with a card type interface or a signal connector interface or alternatively simultaneously combined with a battery module, a storage module, and a wireless transmission module to achieve an advantage of having multiple interfaces. | 04-02-2015 |
20150099382 | MULTIPLE-IN-ONE INTERFACE CONNECTOR - A multiple-in-one interface connector includes a shielding casing, an insulation body received in the shielding casing, a micro card receiving zone formed on a surface of the insulation body and a micro USB connection zone, a card ejection bar movably arranged at one side of the insulation body, and a card ejector rotatably mounted to the insulation body and operatively coupled to the card ejection bar. The insulation body includes a micro card receiving port and a micro USB connection port respectively in the micro card receiving zone and the micro USB connection zone. A micro card and a micro USB male connector can be respectively inserted to the micro card receiving zone and the micro USB connection port. To eject the micro card, the card ejection bar is pushed to move the card ejector so as to eject the micro card out of the micro card receiving zone. | 04-09-2015 |
20160006148 | OBVERSELY AND REVERSELY PLUGGABLE CONNECTOR STRUCTURE - An obversely and reversely pluggable connector structure, includes a multi-plate circuit board, first transmission conductor set and second transmission conductor set each, a plurality of first soldering faces and second soldering faces, a plurality of first conduction portions and second conduction portions, a plurality of first through holes and second through hole portions, a first shielding shell and second shielding shell each, first capacitor unit and second capacitor unit each at least, allowing the first transmission conductor set and second transmission conductor set different in length to clamp a connector to the circuit board together through the above components, and components for soldering, conducting, reducing noise are configured correspondingly to each transmission conductor set, thereby achieving the reduction of the volume upon a connector assembly, and having the effect of decreasing EMI (Electromagnetic interference) and RFI (radio frequency interference). | 01-07-2016 |
20160007445 | HIGH-FREQUENCY SIGNAL PROCESSING METHOD - The high-frequency signal processing method provides at least two isolation terminals between adjacent signal transmission conductor sets. For two adjacent signal transmission conductor sets of a substrate, at least two vias through the substrate are embedded with conductive pillars, respectively. Each conductive pillar penetrates the dielectric layers of the substrate from a top side to a bottom side of the substrate. Each via with the embedded conductive pillar functions as an isolation terminal. The signal transmission conductor sets are as such segregated by the isolation terminals and the isolation terminals provides two layers of shielding. With the present invention, there is no requirement of having a casing and the miniaturization of form factors of the electronic appliances is not compromised. The dual isolation terminals significantly suppress the strength and influence of interference produced by a signal transmission conductor. | 01-07-2016 |
20160079711 | Electronic Connector - An electronic connector includes a transmission conductor group including two rows of spring contacts for insertion into a connector female portion in normal and reverse directions, a transmission conductor pin group, which is formed at a rear side of the transmission conductor group and arranged in a single row, a circuit substrate, which is electrically connected to the transmission conductor pin group, a shielding housing, which receives therein the transmission conductor group, and an inclined cover section, which extends from the shielding housing to shield the transmission conductor pin group. As such, contacts of the transmission conductor group are provided in two rows so that mating between a male portion and a female portion can be made in a directionless manner, allowing for insertion in both normal and reverse directions. The transmission conductor pin group is set in an arrangement of a single row to maintain the convenience of manufacturing. | 03-17-2016 |
20160079712 | Electronic Connector - An electronic connector includes a transmission conductor group including two rows of plate-like contacts for insertion of a connector male portion in normal and reverse directions, a transmission conductor pin group, which is formed at a rear side of the transmission conductor group and arranged in a single row, a shielding housing, which receives therein the transmission conductor group, and an inclined cover section, which extends from the shielding housing to shield the transmission conductor pin group. As such, contacts of the transmission conductor group of the connector are provided in an arrangement of two rows so that mating between a male portion and a female portion can be made in a directionless manner, allowing for insertion in both normal and reverse directions. The transmission conductor pin group extending rearward from the transmission conductor group is set in an arrangement of a single row to maintain the convenience of manufacturing. | 03-17-2016 |
Patent application number | Description | Published |
20120315776 | CONNECTOR ASSEMBLY - A connector assembly adapted to be used in a wrist watch which has data transmission and storage functions, includes a connector including an insulating body and a plurality of terminals each having a soldering tail, and a FPC board acted as a watchstrap of the wrist watch or attached on an initial watchstrap of the wrist watch to electrically connect the connector and a circuit of the wrist watch. Wherein the soldering tails of the terminals are embedded in one end of the FPC board at regular intervals by means of solder press welding, then the one end of the FPC board together with the soldering tails of the terminals are molded in the insulating body as an integral, and the other end of the FPC board is electrically connected with the circuit of the wrist watch. | 12-13-2012 |
20130045615 | CARD CONNECTOR - A card connector is disclosed. The card connector comprises an insulative base, a plurality of connecting terminals, a card ejecting mechanism and a shielding case. The shielding case covers the insulative base. A card insertion region is formed between the insulative base and the shielding case. A plurality of terminal slots is defined on a surface of the insulative base facing the card insertion region. The connecting terminals are received in the terminal slots. The tray comprises an inner tray and an outer tray. The outer tray is pivotally connected to the inner tray. The inner tray and the outer tray are connected together to form a receiving groove for receiving a SIM card. The tray is formed by pivotally connecting the inner tray to the outer tray, therefore, the card connector according to the present invention can be used more conveniently. | 02-21-2013 |
20130078866 | ELECTRICAL CONNECTOR - Disclosed is an electrical connector, which includes an insulative body, a plurality of terminals, and a case. Terminal slots are defined in the insulative body. The terminals are respectively disposed in the terminal slots. The terminals includes a grounding terminal, a power terminal, and a plurality of signal terminals, such that each of the grounding, the power, and the signal terminals has a base arm, a contacting arm, and a welding arm, wherein heights of the contacting arms of the grounding terminal, the power terminal, and the signal terminals are gradually descending to form differences of the heights. Because the heights of the contacting arms are designed to gradually descend, the main control circuit inside a navigator can be better protected, and a more stable signal transmission can be ensured. | 03-28-2013 |
20130090019 | Electrical Connector - An electrical connector includes a first connector which includes a first insulating body and first terminals disposed in the first insulating body with one end thereof being exposed outside for connecting with one external connector, a second connector which includes a second insulating body and second terminals disposed in the second insulating body with one end thereof being exposed outside for connecting with another different external connector, and a shell enclosing the first connector and the second connector and looped from a metal plate with a matching mouth being freely opened for the convenience of the insertion of the external connectors to connect with the first connector or the second connector, wherein the first connector and the second connector are connected together by molding the first insulating body and the second insulating body integrally in a single mold. | 04-11-2013 |
20130210284 | ELECTRICAL CONNECTOR - An electrical connector includes an insulating housing which defines an inserting mouth penetrating through a front side thereof and terminal grooves communicating with the inserting mouth and each extending longitudinally to penetrate rearward through the insulating housing. A plurality of electrical terminals is assembled in the terminal grooves and each has a contact arm elastically stretching into the inserting mouth and defining a contact end. The insulating housing further defines a plurality of through holes penetrating vertically therethrough to connect with the inserting mouth and arranged in accordance with the contact ends of the electrical terminals. The through holes are used to provide action space for meeting movements of the contact ends and receiving the contact ends therein, when a mating part is inserted into the inserting mouth and pressure contacts with the contact ends. | 08-15-2013 |
Patent application number | Description | Published |
20130257283 | ILLUMINATION DEVICE AND ILLUMINATION CONTROL SYSTEM OF THE ILLUMINATION DEVICE - An illumination device obtaining an internet protocol (IP) address from a dynamic host configuration protocol (DHCP) server includes a first sensor, an illumination unit, a processor, and a registered jack 45 (RJ-45) interface. The first sensor is configured to output a first detecting signal with respect to an ambient luminance. The illumination unit includes a lighting module and a driving module capable of controlling operation status of the lighting module. The processor is configured to output a control signal to the driving module according to the first detecting signal. The RJ- | 10-03-2013 |
20130278815 | AUXILIARY FOCUSING SYSTEM AND FOCUSING METHOD - A focusing method for a camera by adjusting the focal length from a minimum focal length to a maximum focal length. Obtaining a number of first image definitions for analysis and comparing the first definitions to obtain a greatest definition in the first definitions. When the camera is adjusted for obtaining a second definition, obtaining a number of second image definitions for analysis. Comparing the second definition with the greatest definition and outputting a first informing signal if the second definition is less than the greatest definition. Informing the user that the camera needs to be adjusted and outputting a second informing signal when the second definition is equal to the greatest definition and informing the user that further adjustment is not required. | 10-24-2013 |
20140176766 | BRIGHTNESS-ADJUSTING SYSTEM AND METHOD THEREOF AND ELECTRONIC DEVICE USING SAME - A brightness-adjusting method is provided. The method includes the following steps: divide the first image into a plurality of sub-images; acquire an average brightness value of each sub-image; detect whether or not the average brightness value of each sub-image falls within a predetermined brightness value range; determine the driving controller associated with the light-emitting unit associated with the sub-image that has an average brightness value that does not fall within the predetermined brightness value range; control the determined driving controller to adjust current flowing to the light-emitting unit to adjust the illumination value of the light-emitting unit; and control the lens module to capture a second image of the object after the driving controller has adjusted the current flowing to the light-emitting unit. A brightness-adjusting system and an electronic device using the same are also provided. | 06-26-2014 |
20140207904 | NETWORK CONNECTION SYSTEM AND METHOD - A network connection method applied between at least one network camera and at least one network storage device is provided. The network connection method includes steps of controlling the at least one network storage device to send inviter information in response to a first instruction, controlling the network camera to receive the inviter information in response to a second instruction, controlling the network camera to send reply information based on the received inviter information, controlling the network storage device to receive the reply information, and connecting the network camera to the network storage device based on the reply information. A related network connection system and a storage medium are also provided. | 07-24-2014 |
20140320727 | ADJUSTMENT APPARATUS FOR CAMERA MODULE - An adjustment apparatus for adjusting a camera lens with an adjustment pin includes a supporting bracket, a gear assembly installed to the supporting bracket, a motor mounted to the supporting bracket, a controller electrically connected to the motor, and an adjustment member movably installed to the supporting bracket. The adjustment member includes two spaced clamping poles clamping the adjustment pin of the camera lens. The controller controls the motor to rotate and the motor drives the gear assembly to rotate, to drive the adjustment member to move. Thereby, the adjustment pin is moved by the clamping pins to adjust the camera lens. | 10-30-2014 |