Patent application number | Description | Published |
20110038202 | CONTROL DRIVER FOR MEMORY AND RELATED METHOD - A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal. | 02-17-2011 |
20120087192 | Non-Volatile Memory Device with Program Current Clamp and Related Method - A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit. | 04-12-2012 |
20120230109 | Method of Setting Trim Codes for a Flash Memory and Related Device - A flash memory device with auto-trimming functionality includes a memory cell array comprising first memory cells and a fuse sector, a read circuit for reading a memory state of the first memory cells, an offset circuit for outputting offset current values, and an auto-trimming circuit. The auto-trimming circuit has a register for storing a current characteristic, a current control module for modifying input current applied to a first memory cell under test at a first address according to the memory state, and updating the current characteristic to the modified input current, an address counter for starting application of the modified input current to a second memory cell at a second address for test when reading the first memory cell passes, and a programming circuit for programming the fuse sector according to the current characteristic and the offset current values. | 09-13-2012 |
20130176808 | WORD LINE BOOST CIRCUIT - A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse. | 07-11-2013 |
20130343126 | FLASH MEMORY APPARATUS WITH REFERENCE WORD LINES - The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result. | 12-26-2013 |
20140006885 | MEMORY ARCHITECTURE AND ASSOCIATED SERIAL DIRECT ACCESS CIRCUIT | 01-02-2014 |
20140016414 | FLASH MEMORY - The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current. | 01-16-2014 |
20140119125 | FLASH MEMORY - The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current. | 05-01-2014 |
20140211562 | FLASH MEMORY AND ASSOCIATED PROGRAMMING METHOD - A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage. | 07-31-2014 |
20140355353 | CURRENT SENSING AMPLIFIER AND SENSING METHOD THEREOF - A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage. | 12-04-2014 |