Patent application number | Description | Published |
20150048297 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode. | 02-19-2015 |
20150137206 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 05-21-2015 |
20150279849 | SILICON NITRIDE (SiN) ENCAPSULATING LAYER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation. | 10-01-2015 |
20150295005 | DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSORS - Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench. | 10-15-2015 |
20150295172 | RRAM Cell with Bottom Electrode - The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell. | 10-15-2015 |
20150340493 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 11-26-2015 |
20150372136 | Pattern Layout to Prevent Split Gate Flash Memory Cell Failure - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided. | 12-24-2015 |
20160049420 | COMPOSITE SPACER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact. | 02-18-2016 |
Patent application number | Description | Published |
20130113872 | VIDEO CONFERENCE SYSTEM - An embodiment provides a video conference system including an audio processing unit, a video processing unit and a network processing unit. The audio processing unit encodes an audio signal to an audio stream. The video processing unit encodes a pause image to a first video stream when the video conference system is in a pause mode, and encodes a video signal to a second video stream when the video conference system is in a conference mode. The network processing unit encodes the first video stream to a first network package in the pause mode, and encodes the second video stream and the audio stream to a second network package in the conference mode. | 05-09-2013 |
20130113873 | VIDEO CONFERENCE SYSTEM - A video conference method, applied to a video conference system in a multi-way conference is provided. The video conference method includes: retrieving a first number of a plurality of terminals of the multi-way conference; determining whether at least one other terminal is requiring to join in on the multi-way conference; when the at least one other terminal is requiring to join in on the multi-way conference, increasing the first number of the terminals of the multi-way conference to a second number of the terminals; and determining a resolution of the video signal captured and transmitted by the video conference system according to the second number of the terminals. A video conference system using the video conference method, is also provided. | 05-09-2013 |
20140348076 | COMMUNICATION SYSTEM AND METHOD - A communication system and method are provided. In the communication system, a first electrical device has an end point which is configured to connect to a plurality of 3G dongles, wherein the 3G dongles have different IP addresses; a cloud server integrates the IP addresses to generate an integrated IP address when the cloud server detects that the first electrical device is connected to the 3G dongles; and a second electrical device transmits data packets with the first electrical device via the integrated IP address through the cloud server. | 11-27-2014 |