Yu, Hsinchu
Ben-Mou Yu, Hsinchu TW
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20080271463 | HEAT PIPE MEASURING SYSTEM - The present invention provides a measuring system to determine the quality of the heat pipe, comprising a heat pipe comprising a first end connected to a first temperature sensor and a second end connected to a second temperature sensor, a heater being connected to said first end and being connected to a multi-function heater controller; a multi-function heater controller being electrically connected to said heater and said one of the first or second temperature sensor, a thermal-electric cooler (TEC) module being connected to said second end; and a TEC controller being electrically connected to said TEC module and said one of the first or second temperature sensor, wherein said TEC controller comprises a proportional-integral-derivative controller, and said multi-function heater controller comprises both constant heating power and constant temperature control modes. | 11-06-2008 |
Bing-Shun Yu, Hsinchu TW
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20090236739 | SEMICONDUCTOR PACKAGE HAVING SUBSTRATE ID CODE AND ITS FABRICATING METHOD - A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code. The complexity of the semiconductor packaging processes is not increased and the circuits of the substrates are not easily damaged. | 09-24-2009 |
Bo-Ren Yu, Hsinchu TW
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20100123529 | MODE CONVERTER AND MICROWAVE ROTARY JOINT WITH THE MODE CONVERTER - A microwave rotary joint comprises a mode converter for converting microwave signals of a TE | 05-20-2010 |
Cheng Yeh Yu, Hsinchu TW
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20090302349 | STRAINED GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - A strained germanium field effect transistor (FET) and method of fabricating the same is related to the strained Ge field effect transistor with a thin and pure Ge layer as a carrier channel. The pure Ge layer with the thickness between 1 nm and 10 nm is formed between an unstrained substrate and a gate insulation layer, and directly contacts with the unstrained substrate. The gate is disposed on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained Ge FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. Furthermore, a Si protective layer with extremely thin thickness can be deposed between and directly contacts with the gate insulation layer and the pure Ge layer. | 12-10-2009 |
Chia-Chin Yu, Hsinchu TW
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20100079245 | RADIO FREQUENCY IDENTIFICATION READER HAVING ANTENNAS IN DIFFERENT DIRECTIONS - A radio frequency identification (RFID) reader includes a plurality of signal antennas, which are respectively arranged in directions that are not parallel to and co-linear with each other. Each of the signal antennas has a predetermined antenna field pattern and operates with a predetermined carrier wave frequency. A wireless receiver is connected to the signal antennas. A signal conversion unit is connected to the wireless receiver. A frequency generator generates the carrier wave frequency to the signal antenna. A microprocessor is connected to the signal conversion unit and the frequency generator. | 04-01-2010 |
20100141385 | HANDHELD ELECTRONIC DEVICE AND MOBILE RFID READER THEREOF - A handheld electronic device and mobile RFID (Radio Frequency Identification) reader equipped thereon allow a user to move to wherever necessary and sense RFID tag data of a target object. The mobile RFID reader includes a microprocessor, a memory unit connected to the microprocessor, a reader positioning unit, a RFID transceiver, a temporary data storage and a network interface. The reader positioning unit positions the location of the RFID reader to obtain reader location information of the RFID reader, and then the RFID transceiver receives a tag signal with tag ID (Identification) data from RFID tag. The reader location information and the tag ID data of the RFID tag are able to be stored optionally in the temporary data storage, and will be uploaded to a backend network sever whenever the RFID reader is connected to the backend network sever through its network interface. | 06-10-2010 |
20100164723 | SYSTEM AND METHOD FOR POSITIONING ACTIVE RFID TAG - A positioning system and method are provided to use multiple RFID readers to position a target object with an active RFID tag equipped thereon. The system and method defines a geometric center of the locations of the RFID readers as a first coordinate. When the RFID readers continuously receive RF signals of the active RFID tag, a corresponding signal intensity of each of the RF signals is calculated and compared to obtain an approaching vector corresponding to the location of the RFID reader with the greatest signal intensity of the RF signal. A positioned location of the target object is then approached from the first coordinate to a second coordinate according to the approaching vector. The first coordinate and the positioned location of the target object will be reset as the second coordinate. The reset first coordinate is output as the latest positioned location of the target object. | 07-01-2010 |
20100188194 | MOBILE RFID MONITORING SYSTEM AND METHOD THEREOF - A mobile RFID (Radio Frequency Identification) system and method are provided to monitor multiple control zones of the system simultaneously through a mobile outpost monitor. The control zones included in the system are connected with each other through a data exchange interface. Each of the control zones includes a link interface connecting with a gateway of at least one RFID tracking module. The gateway connects with at least one RFID reader and a signal transmitter to receive tag information of RFID tags within the control zone, and transmits the tag information through the signal transmitter. When the mobile outpost monitor moves from one control zone to another, the mobile outpost monitor may switch to link with the signal transmitter of the gateway in the current control zone. Through the data exchange interface, the mobile outpost monitor is able to obtain the monitoring information of another control zones. | 07-29-2010 |
20100302095 | SYSTEM FOR SHARING GPS PROTOCOL DATA AND METHOD THEREOF - A system for sharing GPS protocol data is described. In the system, raw GPS protocol data from a satellite is obtained by a GPS receiver. A GPS protocol data server is connected to the GPS receiver through a physical serial port, so as to obtain the GPS protocol data. A service application program is execute on the GPS protocol data server, and provides a service of resolving the GPS protocol data or converting the format thereof through a TCP/IP based multi-thread communication procedure. A virtual serial port driver is used to generate a plurality of virtual serial ports, and each virtual serial port communicates with the service application program through the TCP/IP protocol. Therefore, application devices or application programs respectively communicates with the service application program through the virtual serial ports, thereby obtaining the service of parsing the GPS protocol data provided by the service application program. | 12-02-2010 |
Chia-Da Yu, Hsinchu TW
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20110163300 | ORGANIC LIGHT-EMITTING MATERIAL, ORGANIC LIGHT-EMITTING ELEMENT USING THE SAME AND METHOD OF FORMING THE SAME - The present invention provides compound of formula (I) | 07-07-2011 |
20130137206 | ORGANIC LIGHT-EMITTING MATERIAL, ORGANIC LIGHT-EMITTING ELEMENT USING THE SAME AND METHOD OF FORMING THE SAME - The present invention provides compound of formula (I) | 05-30-2013 |
Chia-Hsin Yu, Hsinchu TW
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20130257808 | OPTICAL TOUCH APPARATUS - An optical touch apparatus includes a base, a light source and a light sensing element. The base is constituted by a bottom wall, a plurality of sidewalls and at least one supporting part. The sidewalls are connected to the bottom wall. The sidewalls and the bottom wall corporately form an accommodation space. The at least one supporting part is connected to at least one of the sidewalls and extends from at least one of the connected sidewall(s) in a direction away from the accommodation space. The light source and the light sensing element are disposed on the at least one supporting part. | 10-03-2013 |
Chien Peng Yu, Hsinchu TW
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20100026266 | PULSE WIDTH MODULATION CONTROLLER, CIRCUIT AND METHOD THEREOF WITH SHORT CIRCUIT PROTECTION - A PWM comprises a voltage transformation module, a voltage-sensing module and a timer. The voltage transformation module is configured to transform an input voltage into an output voltage. The voltage-sensing module is coupled to the voltage transformation module and configured to detect a voltage of a first terminal, wherein the voltage of the first terminal is proportional to the output voltage. The timer is configured to measure the time duration for which the voltage of the first terminal is lower than a reference voltage, wherein the timer initiates a short circuit signal when the time duration is greater than a predetermined value. | 02-04-2010 |
Chien-Ying Yu, Hsinchu TW
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20100013536 | Absolute time delay generating device - An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals. | 01-21-2010 |
Chih-Chieh Yu, Hsinchu TW
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20130146134 | SOLAR CELL WITH NANOLAMINATED TRANSPARENT ELECTRODE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a solar cell with a nanolaminated transparent electrode and a method of manufacturing the same. The solar cell comprises a substrate, a first electrode layer deposited on the substrate, a photovoltaic layer deposited on the first electrode layer, and a second electrode layer deposited on the photovoltaic layer. Wherein, at least one of the first and second electrode layers is a nanolaminated transparent electrode prepared by using atomic layer deposition (ALD). The nanolaminated transparent electrode may serve as both of the transparent electrode and the anti-reflective layer and is able to maintain good transmittance in infrared wavelength. | 06-13-2013 |
20140016104 | PORTABLE ELECTRONIC DEVICE WITH MULTIPLE PROJECTING FUNCTIONS - A portable electronic device with multiple projecting functions is provided. The portable electronic device includes a main body, a projecting module, and a switching mechanism. The projecting module is disposed within the main body for generating an image beam. The switching mechanism is movably disposed on the main body. When the switching mechanism is located at a first position, the image beam is projected along a first projecting path, and the portable electronic device is in a first operating mode. When the switching mechanism is located at a second position, the image beam is projected along a second projecting path, and the portable electronic device is in a second operating mode. | 01-16-2014 |
Chih-Sheng Yu, Hsinchu TW
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20120231464 | Heatable Droplet Device - A heatable droplet device is used to embody real-time detection by means of the device's temperature control and surface treated and trimmed. A temperature causing internal stability disturbed is immediately detected with a designed sensor while affecting a specific area. | 09-13-2012 |
Chi-Min Yu, Hsinchu TW
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20090111361 | METHOD OF SUPPLYING POLISHING LIQUID - The present invention relates to a method of supplying the polishing liquid by periodically interrupt the supply of the polishing liquid, thus avoid over-supply or wastage of the polishing liquid. Hence, the consumption of the polishing liquid can be decreased and the production cost can be lower. | 04-30-2009 |
Chin-Chi Yu, Hsinchu TW
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20130082942 | ELECTRONIC PAPER DISPLAY - An electronic paper display is provided. The electronic paper display includes a first substrate including a thin film transistor layer, and a front panel laminate. The thin film transistor layer is located on a surface of the first substrate. The front panel laminate is located on the thin film transistor layer. The front panel laminate includes a second substrate, a common electrode layer, an electronic ink layer, and a touch sensing electrode layer. The second substrate includes a first surface facing the first substrate, and a second surface facing away from the first surface. The common electrode layer is located on the first surface of the second substrate. The electronic ink layer is located between the thin film transistor layer and the common electrode layer. The touch sensing electrode layer is directly formed on the second surface of the second substrate. | 04-04-2013 |
20140196854 | SEPARATING APPARATUS - A separating apparatus, including a base and a wire, is provided. The base is adapted for carrying an electronic device. The electronic device includes a first substrate, a second substrate, and an adhesive layer. The adhesive layer adheres the first substrate and the second substrate to each other. The wire is configured on the base. A wire diameter of the wire is equal to or greater than a thickness of the adhesive layer. | 07-17-2014 |
Ching-Chou Yu, Hsinchu TW
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20090262064 | LCD AND BACKLIGHT MODULE DRIVING DEVICE AND METHOD THEREOF - An LCD and a backlight module driving device and a method thereof are provided. The method is adapted to drive at least one backlight unit in a backlight module. The backlight unit is used for supplying a surface light source to an N | 10-22-2009 |
Chiu Mei Yu, Hsinchu TW
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20090256831 | Display Apparatus and Circuit Reparation Method Thereof - A display apparatus and a circuit reparation method thereof are provided. The display apparatus comprises a control module, a first gate on array (GOA) circuit, a second GOA circuit, and a variable voltage source. The control module generates at least one control signal. The first GOA circuit is electrically connected to the control module according to a first leading wire in advance. The second GOA circuit is electrically connected to the control module according to a second leading wire in advance. The variable voltage source provides a predetermined voltage level. When the first GOA circuit is disabled, the first GOA circuit and the control module are adjusted to be electrically disconnected, and the first leading wire is electrically connected to the variable voltage source. The display apparatus is operated in response to the control signal and the predetermined voltage level. | 10-15-2009 |
Chou-Huan Yu, Hsinchu TW
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20110053323 | PHOTOMASK AND METHOD FOR FABRICATING SOURCE/DRAIN ELECTRODE OF THIN FILM TRANSISTOR - A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed. | 03-03-2011 |
20120270397 | Photomask and Method for Fabricating Source/Drain Electrode of Thin Film Transistor - A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode. | 10-25-2012 |
Chung Chih Yu, Hsinchu TW
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20110293156 | METHOD AND COMPUTER FOR AIDING DETERMINATION OF OBSTRUCTIVE SLEEP APNEA - A computer for aiding determination of Obstructive Sleep Apnea (OSA) includes a storage device storing with a medical image and a central processing unit (CPU). The CPU executes a method for aiding determination of OSA. The method for aiding determination of OSA includes the following steps. The medical image is obtained. An upper airway model is established. A narrowest cross-section and a nasopharyngeal boundary cross-section are defined in the airway model. A cross-sectional area of the narrowest cross-section and a cross-sectional area of the nasopharyngeal boundary cross-section are calculated. A stenosis rate is calculated according to the cross-sectional area of the narrowest cross-section and the cross-sectional area of the nasopharyngeal boundary cross-section. The stenosis rate is provided. In addition, in the method for aiding determination of OSA, a respiratory flow field simulation may be further performed to obtain and provide a flow field pressure distribution of the upper airway model. | 12-01-2011 |
Chung-Shan Yu, Hsinchu TW
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20110245088 | AMIDE-BASED SOLUTION-PHASE DERIVED LIBRARY AND METHOD FOR SCREENING THEREOF - An amide-based library is disclosed in the invention which is prepared via amide bond formation coupling an amine with a carboxylic acid. Also, a method using said library for screening a drug candidate is provided in the present invention. Compounds in the present invention having cytotoxicities are useful for a variety of therapeutic applications. | 10-06-2011 |
20110306668 | CONSTRUCTION AND SCREENING OF SOLUTION-PHASE DERIVED LIBRARY OF FENBUFEN AND ETHACRYNIC ACID - A process for synthesizing and screening solution phase derived libraries of fenbufen and ethacrynic acid is provided in the present invention. Compounds in the present invention having cytotoxicities are useful for a variety of therapeutic applications. | 12-15-2011 |
20130156701 | METHOD OF PREPARING ETHACRYNIC AMIDE DERIVATIVES AND APPLICATION THEREOF - The present invention provides a method for preparing [ | 06-20-2013 |
20140079633 | METHOD OF PREPARING [123I]IODOOCTYL FENBUFEN AMIDE AND APPLICATION THEREOF - The present invention provides a method of preparing [ | 03-20-2014 |
Chun-Ta Yu, Hsinchu TW
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20130320296 | LIGHT EMITTING DEVICE WITH QCSE-REVERSED AND QCSE-FREE MULTI QUANTUM WELL STRUCTURE - A light-emitting device comprises a semiconductor stacked structure, the semiconductor stacked structure comprising a p-type semiconductor layer, a n-type semiconductor layer and an multiple quantum well structure between the p-type semiconductor layer and the n-type semiconductor layer, wherein the multiple quantum well structure comprises a first multiple quantum well structure near the n-type semiconductor layer and a second multiple quantum well structure near the p-type semiconductor layer, wherein the first multiple quantum well structure has positive interface bound charge and the second multiple quantum well structure has zero interface bound charge. | 12-05-2013 |
20140117306 | Light Emitting Device - A light-emitting device comprises a first type semiconductor layer, a multi-quantum well structure on the first type semiconductor layer, and a second type semiconductor layer on the multi-quantum well structure, wherein the multi-quantum well structure comprises a first portion near the first type semiconductor layer, a second portion near the second type semiconductor layer, and a strain releasing layer between the first portion and the second portion and comprising a first layer including Indium, a second layer including Aluminum on the first layer, and a third layer including Indium on the second layer, wherein the Indium concentration of the third layer is higher than that of the first layer. | 05-01-2014 |
20140167097 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating an optoelectronic device comprising, providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a semiconductor epitaxial stack on the first major surface including a first conductive-type semiconductor layer having a first doping concentration, an active layer, and a second conductive-type semiconductor layer wherein the semiconductor epitaxial stack having four boundaries and a geometric center; and forming a plurality of the hollow components in the first conductive-type semiconductor layer wherein the plurality of the hollow components is formed from the boundary of the semiconductor epitaxial stack to the geometric center of the semiconductor epitaxial stack. | 06-19-2014 |
20140217358 | LIGHT-EMITTING DIODE AND THE MANUFACTURE METHOD OF THE SAME - This application discloses a light-emitting diode comprising a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a semiconductor contact layer on the second semiconductor layer. The second semiconductor layer comprises a first sub-layer and a second sub-layer formed above the first sub-layer, wherein the material of the second sub-layer comprises Al | 08-07-2014 |
Gordon Yu, Hsinchu TW
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20110055450 | Multifunctional Storage Device with Built-in Software Controlled I/O Bus - A multifunctional storage device with a built-in software controlled I/O bus includes a transmission interface plug, a transmission interface hub, at least one I/O device, at least one bridge and a built-in storage device. The built-in storage device includes a memory controller and a memory module, and the memory module stores a software program and an auto-run setup program for automatically controlling and turning on or off connected to at least one I/O device (such as an extended device including a built-in device and an external device) of the bridge, such that a user can save the trouble of installing complicated driver programs and performing a manual setup to achieve a real plug-and-play function. | 03-03-2011 |
Hsiu-Mei Yu, Hsinchu TW
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20080251916 | UBM structure for strengthening solder bumps - A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon. | 10-16-2008 |
20080303154 | Through-silicon via interconnection formed with a cap layer - An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask. | 12-11-2008 |
20100013059 | DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES - The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench. | 01-21-2010 |
20110241179 | DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES - The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench. | 10-06-2011 |
Hsu Sheng Yu, Hsinchu TW
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20110074030 | METHOD FOR PREVENTING Al-Cu BOTTOM DAMAGE USING TiN LINER - A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines | 03-31-2011 |
Hui-Lung Yu, Hsinchu TW
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20090213043 | METHOD FOR DRIVING DISPLAY PANEL - A method for driving a display panel includes generating data signals to drive pixels in the display panel. The pixels in the display panel are arranged in a matrix. In addition, the voltage values of the data signals are adjusted to render a sum of voltage values of the data signals in a unit area as zero. | 08-27-2009 |
Hung-Chang Yu, Hsinchu TW
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20120127806 | MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor. | 05-24-2012 |
20120134218 | CHARGE PUMP CONTROL SCHEME USING FREQUENCY MODULATION FOR MEMORY WORD LINE - A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage. | 05-31-2012 |
20120134228 | CHARGE PUMP CONTROL SCHEME FOR MEMORY WORD LINE - A memory includes a word line, a charge pump coupled to the word line, and a charge pump control circuit coupled to the charge pump. The charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage and turn off the charge pump if the word line voltage is higher than a second threshold voltage. | 05-31-2012 |
20130121088 | MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness. | 05-16-2013 |
20130127515 | VOLTAGE DIVIDING CIRCUIT - A voltage divider is disclosed that includes a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals. The voltage divider also includes a level shifter having a input terminal coupled to the reference voltage node and having a output terminal supplying an output reference voltage. | 05-23-2013 |
20140211537 | RESISTANCE-BASED RANDOM ACCESS MEMORY - A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node. | 07-31-2014 |
20140340970 | MEMORY WITH DYNAMIC FEEDBACK CONTROL CIRCUIT - A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage. | 11-20-2014 |
Hung-Hsiu Yu, Hsinchu TW
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20090058673 | Information communication and interaction device and method for the same - An information communication and interaction device and method for the same are disclosed according to the present invention; the device is applicable to data processing device that can run the information communication software and has first data transmission unit; the data processing device is capable of processing information communication and sharing by using the information communication software through one data transmission system; features of the method of the present invention are: have one control unit process information communication with data processing device through one second data transmission unit, which is connecting to the first data transmission unit; and based on coded datum of the communicated information, the control unit commands one drive unit to drive one motion unit to bring about a real motion corresponding to the information; therefore, signified conception of the information can be expressed properly by means of real interaction. | 03-05-2009 |
20090091470 | INFORMATION COMMUNICATION AND INTERACTION DEVICE AND METHOD FOR THE SAME - An information communication and interaction device and a method for the same are disclosed. The device is applicable to a data processing device that can run information communication software and has first data transmission unit. The data processing device is capable of processing information communication and sharing by using the information communication software through a data transmission system. According to the method, a control unit processes information communication with the data processing device through a second data transmission unit, which is connected to the first data transmission unit, and based on coded data of the communicated information, the control unit commands a drive unit to drive a motion unit to bring about a real motion corresponding to the information. Therefore, signified conception of the information can be expressed properly by means of real interaction. | 04-09-2009 |
20100235451 | INSTANT MESSAGING INTERACTION SYSTEM AND METHOD THEREOF - An instant messaging interaction system and method work by: analyzing communicative information sent by a remote user to create emotional messages and analyzing information about the remote user's identity; storage in a storage module behavior weight value preset and corresponding to the information about the remote user's identity; determining, by a learning module, interactive responses according to the emotional messages and the behavior weight values; outputting, by an output module, the interactive responses; detecting if receiving a feedback signal from an local user; if the feedback signal is not received, the learning module stores the behavior weight value in the storage module; if the feedback signal is received, the feedback module generates a modification value corresponding to different levels of the feedback signal; generating, by the learning module and according to a detection result, modification values for modifying the behavior weight values. As a result, the messaging interaction system is capable of presenting rated interactive responses in a personalized, artificial intelligence-based manner that meets the local user's expectation. | 09-16-2010 |
Jeng-Wei Yu, Hsinchu TW
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20120264246 | Method of Selective Photo-Enhanced Wet Oxidation for Nitride Layer Regrowth on Substrates - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation. | 10-18-2012 |
20120264247 | Method of Separating Nitride Films from the Growth Substrates by Selective Photo-Enhanced Wet Oxidation - Various embodiments of the present disclosure pertain to separating nitride films from growth substrates by selective photo-enhanced wet oxidation. In one aspect, a method may transform a portion of a III-nitride structure that bonds with a first substrate structure into a III-oxide layer by selective photo-enhanced wet oxidation. The method may further separate the first substrate structure from the III-nitride structure. | 10-18-2012 |
20130228807 | METHOD OF SEPARATING NITRIDE FILMS FROM GROWTH SUBSTRATES BY SELECTIVE PHOTO-ENHANCED WET OXIDATION AND ASSOCIATED SEMICONDUCTOR STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a semiconductor structure may comprise: a first substrate structure; a III-nitride structure bonded with the first substrate structure; a plurality of air gaps formed between the first substrate structure and the III-nitride structure; and a III-oxide layer formed on surfaces around the air gaps, wherein a portion of the III-nitride structure including surfaces around the air gaps is transformed into the III-oxide layer by a selective photo-enhanced wet oxidation, and the III-oxide layer is formed between an untransformed portion of the III-nitride structure and the first substrate structure. | 09-05-2013 |
20140131750 | METHOD OF SELECTIVE PHOTO-ENHANCED WET OXIDATION FOR NITRIDE LAYER REGROWTH ON SUBSTRATES AND ASSOCIATED STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation. | 05-15-2014 |
20140252308 | METHOD OF SELECTIVE PHOTO-ENHANCED WET OXIDATION FOR NITRIDE LAYER REGROWTH ON SUBSTRATES AND ASSOCIATED STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation. | 09-11-2014 |
Jian-Shen Yu, Hsinchu TW
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20100033208 | SHIFT REGISTER UNITS, DISPLAY PANELS UTILIZING THE SAME, AND METHODS FOR IMPROVING CURRENT LEAKAGE THEREOF - A shift register comprising at least one shift register unit. The shift register unit comprises an input unit, at least one first TFT, and at least one second TFT. The input unit receives an input signal from the input terminal and outputs a switching control signal in accordance with a first clock signal. The gate of the first TFT is for receiving the switching control signal, the drain of the first TFT is for receiving a second clock signal, and the source of the first TFT is coupled to the output terminal. The gate and drain of the second TFT are coupled to the output terminal, and the source of the second TFT is coupled to the input unit. | 02-11-2010 |
20110115718 | MULTI-CHANNEL TOUCH PANEL - The present invention relates to a multi-channel touch panel. In one embodiment, the multi-channel touch panel includes a plurality of driving electrodes spatial-separately arranged in the form of a matrix, a plurality of sensing electrodes associated with the plurality of driving electrodes such that each sensing electrode is surrounded by a corresponding driving electrode, N driving lines spatial-separately arranged along a row direction and M pairs of sensing lines spatial-separately arranged crossing over the N driving lines along a column direction, where each driving electrode in the row of the electrode matrix is electrically connected to each other by a corresponding driving line, and each odd sensing electrode in a column of the electrode matrix is electrically connected to each other by a first sensing line of the corresponding paired sensing lines, and each even sensing electrode in the column of the electrode matrix is electrically connected to each other by a second sensing line of the corresponding paired sensing lines. | 05-19-2011 |
Jui-Yi Yu, Hsinchu TW
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20090256883 | MAINTENANCE STATION OF AN INKJET PRINTER - A maintenance station of an inkjet printer mounted in a housing of the inkjet printer includes an ink cup rotationally and slidably coupled to the housing about/along an axis of rotation. The ink cup has a basic plate and a columnar rim around the basic plate. The columnar rim respectively defines a plurality of stopping ratchets and driving ratchets with the same gradient direction at a bottom and top thereof. A moving body is slidably disposed in the housing of the inkjet printer. An actuator movably disposed in the moving body moves together with the moving body, a tail of the actuator stretches out from the moving body for matching with the driving ratchets to rotate the ink cup. A plurality of housing ratchets are disposed in the housing of the inkjet printer and arranged into a ring for matching with the stopping ratchets to prevent the ink cup reversion. | 10-15-2009 |
Jui-Yuan Yu, Hsinchu TW
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20090278617 | Crystal-less Communications Device and Self-Calibrated Embedded Virtual Crystal Clock Generation Method - This invention discloses a crystal-less communication device and self-calibrated embedded virtual crystal clock generation method. In communication systems, the invention proposes a crystal-less scheme in the device for wireless or wired-line communications. The operation concepts are that the transmitter Device- | 11-12-2009 |
20100013533 | DIGITAL DELAY LINE AND APPLICATION THEREOF - A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power. | 01-21-2010 |
20100013536 | Absolute time delay generating device - An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals. | 01-21-2010 |
Jung-Chuan Yu, Hsinchu TW
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20080274508 | Expression system for enhancing solubility and immunogeneicity of recombinant proteins - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein. The chimeric protein contains three polypeptidyl fragments: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein that contains a protein transduction domain (PTD) or a fragment thereof having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment that contains a J-domain or a fragment thereof having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment that contains a target protein or polypeptide. | 11-06-2008 |
20090187004 | EXPRESSION SYSTEM FOR ENHANCING SOLUBILITY AND IMMUNOGENEICITY OF RECOMBINANT PROTEINS - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein comprising: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein, containing a protein transduction domain (PTD), or a fragment thereof, having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment, containing a J-domain, or a fragment thereof, having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment, containing a target protein or polypeptide. | 07-23-2009 |
Kuo-Chi Yu, Hsinchu TW
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20090104361 | Method of preparartion of a MWCNT/Polymer composite having electromagnetic interference shielding effectiveness - A method of preparing carbon nanotube/polymer composite having electromagnetic interference (EMI) shielding effectiveness is disclosed, which includes: dispersing multi-walled carbon nanotubes (MWCNT) in an organic solvent such as N,N-Dimethylacetamide (DMAc); dissolving monomers such as methyl methacrylate (MMA) and an initiator such as 2,2-azobisisobutyronitrile (AIBN) in the MWCNT dispersion; and polymerizing the monomers in the resulting mixture at an elevated temperature such as 120° C. to form a MWCNT/PMMA composite. The composite is coated onto a PET film, and the coated PET film alone or a stack of multiple coated PET films can be applied as an EMI shielding material. | 04-23-2009 |
20100136327 | Method of preparation of a MWCNT/polymer composite having electromagnetic interference shielding effectiveness - The present invention provides a modified carbon nanotube having —C(O)—R′ or —C(O)—R—COOH covalently bounded to a surface of carbon nanotube, wherein R′ is C1-C26 alkyl or C2-C26 alkenyl, and R is C1-C26 alkylene or C2-C26 alkenylene. The present invention also discloses a carbon nanotubes/polymer composite having electromagnetic interference shielding effectiveness, which contains 0.1-10% of modified carbon nanotubes, based on the weight of the polymer. The present invention further provides methods for preparing the modified carbon nanotubes and the composite. | 06-03-2010 |
20110200740 | METHOD OF PREPARATION OF A MWCNT/ POLYMER COMPOSITE HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING EFFECTIVENESS - A method of preparing carbon nanotube/polymer composite having electromagnetic interference (EMI) shielding effectiveness is disclosed, which includes: dispersing multi-walled carbon nanotubes (MWCNT) in an organic solvent such as N,N-Dimethylacetamide (DMAc); dissolving monomers such as methyl methacrylate (MMA) and an initiator such as 2,2-azobisisobutyronitrile (AIBN) in the MWCNT dispersion; and polymerizing the monomers in the resulting mixture at an elevated temperature such as 120° C. to form a MWCNT/PMMA composite. The composite is coated onto a PET film, and the coated PET film alone or a stack of multiple coated PET films can be applied as an EMI shielding material. | 08-18-2011 |
Kuo-Feng Yu, Hsinchu TW
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20130119480 | INTEGRATED CIRCUIT RESISTOR - A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided. | 05-16-2013 |
20130157452 | SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF - A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. | 06-20-2013 |
Kuo-Hao Yu, Hsinchu TW
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20080313451 | DATA RECOVERY METHOD - The present invention provides a data recovery method in a system with storage of default values and prior configuration values, including executing initialization of the system; loading the default values; detecting a status of a first flag to generate a first detection result; and, determining whether a boot-up sequence is complete according to the first detection result. | 12-18-2008 |
Kuo-Hui Yu, Hsinchu TW
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20090065794 | Light emitting diode device and manufacturing method therof - A light-emitting diode (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first type conductivity semiconductor layer, an active layer, a second type conductivity semiconductor layer, a transparent conductive oxide stack structure, a first electrode, and a second electrode. The first semiconductor layer on the substrate has a first portion and a second portion. The active layer and the second semiconductor layer are subsequently set on the first portion. The transparent conductive oxide stack structure on the second semiconductor layer has at least two resistant interfaces. The first electrode is above the second portion, and the second electrode is above the transparent conductive oxide stack structure. | 03-12-2009 |
20110006701 | LIGHT-EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first type conductivity semiconductor layer, an active layer, a second type conductivity semiconductor layer, a transparent conductive oxide stack structure, a first electrode, and a second electrode. The first semiconductor layer on the substrate has a first portion and a second portion. The active layer and the second semiconductor layer are subsequently set on the first portion. The transparent conductive oxide stack structure on the second semiconductor layer has at least two resistant interfaces. The first electrode is above the second portion, and the second electrode is above the transparent conductive oxide stack structure. | 01-13-2011 |
Li-Chieh Yu, Hsinchu TW
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20140012975 | COMPUTER CLUSTER, MANAGEMENT METHOD AND MANAGEMENT SYSTEM FOR THE SAME - A computer cluster includes a node and a management system. The node includes an agent and generates a node event message in response to occurrence of an event. The agent gathers a software behavior information set, and generates a node information set when the node generates the node event message. The management system is configured to communicate with the node and includes a database storing at least one pre-established solution information set, and an agent management module configured to search the database according to the node information set. Upon finding a solution information set from the database, the agent management module sends the solution information set to the node so that the agent generates a solution for the event. | 01-09-2014 |
Ling-Hao Yu, Hsinchu TW
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20110141864 | TILT CONTROL METHOD OF NEAR-FIELD OPTICAL SYSTEM - A tilt control method for a near-field optical disc drive is provided. A gap between a lens and a disc is estimated. A tilt compensation for the lens is estimated according to a tilt signal when the lens is within a far-field region. A coarse tilt control is performed on the lens according to the tilt compensation when the lens is within the far-field region. | 06-16-2011 |
Ming-Shih Yu, Hsinchu TW
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20110156777 | CLOCK AND DATA RECOVERY CIRCUIT WITH PROPORTIONAL PATH - A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path. | 06-30-2011 |
Ping Hsun Yu, Hsinchu TW
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20090230543 | Semiconductor package structure with heat sink - A semiconductor package structure with a heat sink is disclosed herein. The semiconductor package structure includes a substrate having a chip mounting area and a plurality of through holes surrounding the chip mounting area; a chip set on the chip mounting area and electrically connected to the substrate; a heat sink covering the chip, wherein the heat sink has a plurality of support portions extending from the upper surface to the lower surface of the substrate via those through holes; and a molding compound covering the chip, a portion of the substrate and the heat sink. Those support portions of the heat sink are utilized to improve the heat dissipation efficiency and the warpage issue of the package. | 09-17-2009 |
Po-Hao Yu, Hsinchu TW
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20110291714 | Phase-Locked Loop With Novel Phase Detection Mechanism - A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to D2A module, D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection does not rely on edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input, as opposed to the aforementioned fixed external source, such as, a crystal. | 12-01-2011 |
Shan-Pu Yu, Hsinchu TW
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20090156001 | Structure for reducing stress for vias and fabricating method thereof - A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block. | 06-18-2009 |
Shawn Yu, Hsinchu TW
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20100032447 | PROBE COVER DISPENSER - The present invention discloses a probe cover dispenser, which comprises a base having a probe cover basin; a probe cover cartridge receiving probe covers; a gravitational member applying gravity to the probe covers; and a feeder assembly arranged between the base and the probe cover cartridge. The gravitational member makes a probe cover fall from the probe cover cartridge onto the base, and a feeder pushes the gravitationally released probe cover to the probe cover basin. Then, the user inserts a probe of an infrared thermometer into the probe cover inside the probe cover basin to sleeve the probe with the probe cover. Via the present invention, the user can fit a probe cover onto a probe without using his hands. Thus, the present invention can effectively reduce the pollution of probe covers and the infection of testees. | 02-11-2010 |
Sheng-Jen Yu, Hsinchu TW
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20090145741 | Method for catalytic treating perfluorocompound gas including particle removing unit - The present invention relates to a method for treating fluoro-containing and silicon-containing gas. The method comprises treating the gas with thermal-treating, particles-treating, catalyst-treating, and acid-removing sequentially to remove perfluorocompounds. The invention achieves results of reducing the working temperature, increasing the lifetime of the catalyst, reducing the operating cost of the system, and increasing the applications of the catalyst in the aspect of fluoride-containing gas, silicon-containing gas and particles containing gas treatment by sequential treating. | 06-11-2009 |
20120058033 | METHOD FOR CATALYTIC TREATING PERFLUOROCOMPOUND GAS INCLUDING PARTICLE REMOVING UNIT - The present invention relates to a method for treating fluoro-containing and silicon-containing gas. The method comprises treating the gas with thermal-treating, particles-treating, catalyst-treating, and acid-removing sequentially to remove perfluorocompounds. The invention achieves results of reducing the working temperature, increasing the lifetime of the catalyst, reducing the operating cost of the system, and increasing the applications of the catalyst in the aspect of fluoride-containing gas, silicon-containing gas and particles containing gas treatment by sequential treating. | 03-08-2012 |
Shih-Yuan Yu, Hsinchu TW
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20090140650 | LIGHT-EMITTING DEVICE - A light-emitting device includes a package housing, at least one light-emitting element, a plurality miniature elements, and a package filler. The package housing includes a recess. The light-emitting element is disposed in the recess. The miniature elements are formed on the light-emitting element. Light from the light-emitting element is output to the exterior of the recess in a predetermined direction by adjustment of the miniature elements. The package filler is filled in the recess and covers the light-emitting element and miniature elements. | 06-04-2009 |
Shinn-Sheng Yu, Hsinchu TW
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20100183961 | INTEGRATED CIRCUIT LAYOUT DESIGN - Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element. | 07-22-2010 |
20100201961 | System For Improving Critical Dimension Uniformity - A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({F | 08-12-2010 |
20100203734 | METHOD OF PITCH HALVING - The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element. | 08-12-2010 |
20110151359 | INTEGRATED CIRCUIT LAYOUT DESIGN - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 06-23-2011 |
20120021589 | METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 01-26-2012 |
20120244460 | MECHANISMS FOR PATTERNING FINE FEATURES - The embodiments described provide mechanisms for patterning features for advanced technology nodes with extreme ultraviolet lithography (EUVL) tools. One or more EUV pre-masks are generated by using a mask writer to form an EUV mask with an EUV scanner. The wafers are then patterned by using the EUV mask. The demagnification factor of the EUV scanner(s) used in preparing the EUV mask by exposing the EUV pre-mask(s) enable the wafers prepared by such mechanisms to meet the requirements for the advanced technology nodes. | 09-27-2012 |
20130260288 | EXTREME ULTRAVIOLET LITHOGRAPHY PROCESS AND MASK - A process of an extreme ultraviolet lithography (EUVL) is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask with multiple states. Different states of the EUV mask are assigned to adjacent polygons and a field. The EUV mask is exposed by a nearly on-axis illumination (ONI) with partial coherence σ less than 0.3 to produce diffracted lights and non-diffracted lights. Most of the non-diffracted lights are removed. The diffracted lights and the not removed non-diffracted lights are collected and directed to expose a target by a projection optics box. | 10-03-2013 |
20130280643 | REFLECTIVE MASK AND METHOD OF MAKING SAME - A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, the second absorption layer deposited inside the border ditch, and the second absorption layer contacts the capping layer. | 10-24-2013 |
20140038086 | Phase Shift Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same - A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate, an Ag | 02-06-2014 |
20140038090 | Extreme Ultraviolet Lithography Mask and Multilayer Deposition Method for Fabricating Same - A mask, method of fabricating same, and method of using same are disclosed. In an example, a mask includes a substrate and a reflective multilayer coating deposited over the substrate. The reflective multilayer coating is formed by positioning the substrate such that an angle α is formed between a normal line of the substrate and particles landing on the substrate and rotating the substrate about an axis that is parallel with a landing direction of the particles. In an example, reflective multilayer coating includes a first layer and a second layer deposited over the first layer. A phase defect region of the reflective multilayer coating includes a first deformation in the first layer at a first location, and a second deformation in the second layer at a second location, the second location laterally displaced from the first location. | 02-06-2014 |
20140065521 | METHOD FOR MASK FABRICATION AND REPAIR - A method for repairing phase defects for an extreme ultraviolet (EUV) mask is disclosed. The method includes receiving a patterned EUV mask with at least one phase-defect region, determining location and size of the phase-defect region, depositing an absorber material to cover the phase-defect region and removing a portion of the patterned absorption layer near the phase-defect region in the patterned EUV mask to form an absorber-absent region. | 03-06-2014 |
20140113222 | Mask for Use in Lithography - A mask, or photomask, is used in lithography systems and processes. The mask includes a first polygon of a first state and a second polygon of a second state. The mask also includes a field of the first state and a third polygon of the second state, and in the field. The first and second states are different, and the first and second polygons are located outside of the field. | 04-24-2014 |
20140218713 | Extreme Ultraviolet Lithography Process - A process of an extreme ultraviolet lithography is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask, an EUV radiation source and an illuminator. The process also includes exposing the EUV mask by a radiation, originating from the EUV radiation source and directed by the illuminator, with a less-than-three-degree chief ray angle of incidence at the object side (CRAO). The process further includes removing most of the non-diffracted light and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target. | 08-07-2014 |
20140253892 | Extreme Ultraviolet Lithography Projection Optics System and Associated Methods - The present disclosure provides an extreme ultraviolet lithography system. The extreme ultraviolet lithography system includes a projection optics system to image a pattern of a mask on a wafer. The projection optics system includes between two to five mirrors. The two to five mirrors are designed and configured to have a numerical aperture less than about 0.50, an image field size at the wafer hat is greater than or equal to about 20 mm, and a pupil plane that includes central obscuration. In an example, the central obscuration has a radius that is less than or equal to 50% of a radius of the pupil plane. In an example, the central obscuration has an area that is less than or equal to 25% of an area of the pupil plane. | 09-11-2014 |
20140268086 | Extreme Ultraviolet Lithography Process and Mask - The present disclosure is directed towards lithography processes. In one embodiment, a patterned mask is provided. An information of a position of diffraction light (PDL) on a pupil plane of a projection optics box (POB) is used to define as a light-transmitting region of a pupil filter. The patterned mask is exposed by an on-axis illumination (ONI) with partial coherence σ less than 0.3. The pupil filter is used to transmit diffraction light to a target. | 09-18-2014 |
20140268087 | Lithography and Mask for Resolution Enhancement - A lithography process in a lithography system includes loading a mask having multiple mask states and having a mask pattern consisting of a plurality of polygons and a field. Different mask states are assigned to adjacent polygons and the field. The lithography process further includes configuring an illuminator to generate an illumination pattern on an illumination pupil plane of the lithography system; configuring a pupil filter on a projection pupil plane of the lithography system with a filtering pattern determined according to the illumination pattern; and performing an exposure process to a target with the illuminator, the mask, and the pupil filter. The exposure process produces diffracted light and non-diffracted light behind the mask and the pupil filter removes most of the non-diffracted light. | 09-18-2014 |
20140268091 | Extreme Ultraviolet Lithography Process and Mask - A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. The system and process includes receiving a mask with two states, which have 180 degree phase difference to each other. These different states are assigned to adjacent main polygons and adjacent assist polygons of the mask. A nearly on-axis illumination (ONI) with partial coherence σ less than 0.3 is utilized to expose the mask to produce diffracted lights and non-diffracted lights. A majority portion of the non-diffracted lights and diffracted light with diffraction order higher than 1 are removed. Diffracted light having +1-st and −1-st diffracted order are collected and directed by a projection optics box (POB) to expose a target. | 09-18-2014 |
20140268092 | Extreme Ultraviolet Lithography Process and Mask - A process of an extreme ultraviolet lithography (EUVL) is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask with multiple states. These different states of the EUV mask are assigned to adjacent polygons and adjacent assist polygons. The EUV mask is exposed by a nearly on-axis illumination (ONI) with partial coherence σ less than 0.3 to produce diffracted lights and non-diffracted lights. Most of the non-diffracted lights reflected from main polygons and reflected lights from assist polygons are removed. The diffracted lights and the not removed non-diffracted lights reflected from main polygons are collected and directed to expose a target by a projection optics box. | 09-18-2014 |
20140272678 | Structure and Method for Reflective-Type Mask - The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer formed on the substrate; a capping layer formed on the reflective multilayer and having a hardness greater than about 8; and an absorber layer formed on the capping layer and patterned according to an integrated circuit layout. | 09-18-2014 |
20140272679 | Extreme Ultraviolet Lithography Process and Mask - An extreme ultraviolet lithography (EUVL) process is disclosed. The process comprises receiving a mask. The mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML) over one surface of the LTEM substrate, a first region having a phase-shifting layer over the reflective ML, and a second region having no phase-shifting layer over the reflective ML. The EUVL process also comprises exposing the mask by a nearly on-axis illumination with partial coherence less than 0.3 to produce diffracted light and non-diffracted light, removing at least a portion of the non-diffracted light, and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target. | 09-18-2014 |
20140272680 | Method For Mask Fabrication And Repair - A method for repairing a phase-defect region in a patterned mask for extreme ultraviolet lithography (EUVL) is disclosed. A patterned mask for EUVL is received. The patterned mask includes an absorptive region having an absorption layer over a defect-repairing-enhancement (DRE) layer, a reflective region having the DRE layer without the absorption layer on top of it, a defect and a phase-defect region resulting from the defect and intruding the reflective region. A location and a shape of the phase-defect region is determined. A portion or portions of the DRE layer in the reflective region is removed according to the location and the shape of the phase-defect region to compensate the effect of the phase-defect region. | 09-18-2014 |
20140272682 | Extreme Ultraviolet Lithography Process and Mask - The present disclosure is directed towards an extreme ultraviolet (EUV) mask. The EUV mask includes a low thermal expansion material (LTEM) substrate. The EUV mask has a first region and a second region. The EUV mask also includes a structure disposed in the first region. The structure has a multiple facets with an angle to each other. The EUV mask also includes a conformal reflective multilayer (ML) disposed over the structure in the first region and over the LTEM substrate in the second region. The conformal reflective ML has a similar surface profile as the structure in the first region and a flat surface profile in the second region. | 09-18-2014 |
20140272683 | Method Of Fabricating Mask - A method for fabricating an extreme ultraviolet (EUV) mask includes providing a low thermal expansion material (LTEM) layer. A reflective multiple-layer (ML) is deposited over the LTEM layer. A flowable-photosensitive-absorption-layer (FPhAL) is spin coated over the reflective ML. The FPhAL is patterned by a lithography process to form a patterned absorption layer. | 09-18-2014 |
20140272686 | Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same - A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate and a patterned absorption layer disposed over the reflective multilayer. The patterned absorption layer has a mask image region and a mask border region. The exemplary mask also includes a mask border frame disposed over the mask border region. The mask border frame has a top surface and a bottom surface. The top surface is not parallel to the bottom surface. | 09-18-2014 |
20140272718 | Lithography Process - A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers. | 09-18-2014 |
20140272720 | Multiple Exposures in Extreme Ultraviolet Lithography - An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method comprises providing at least two mask areas having a same pattern, forming a resist layer over a substrate, determining an optimized exposure dose based on an exposure dose for a pre-specified pattern on one of the at least two mask areas to achieve a pre-specified target dimension under a corresponding single exposure process, and performing a multiple exposure process for exposing a same area of the resist layer to the same pattern. The multiple exposure process comprises a plurality of exposure processes, wherein each of the plurality of exposure processes uses an exposure dose that is less than the optimized exposure dose and a sum of the exposure dose of each of the plurality of exposure processes is approximately equal to the optimized exposure dose. | 09-18-2014 |
20140272721 | Extreme Ultraviolet Lithography Process and Mask - An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose. | 09-18-2014 |
20140285789 | Lithography Method and Structure for Resolution Enhancement with a Two-State Mask - A lithography process in a lithography system includes loading a mask that includes two mask states defining an integrated circuit (IC) pattern. The IC pattern includes a plurality of main polygons, wherein adjacent main polygons are assigned to different mask states; and a background includes a field in one of the mask states and a plurality of sub-resolution polygons in another of the two mask states. The lithography process further includes configuring an illuminator to generate an illuminating pattern on an illumination pupil plane of the lithography system; configuring a pupil filter on a projection pupil plane of the lithography system with a filtering pattern determined according to the illumination pattern; and performing an exposure process to a target with the illuminator, the mask, and the pupil filter. The exposure process produces diffracted light and non-diffracted light behind the mask and the pupil filter removes most of the non-diffracted light. | 09-25-2014 |
20140342272 | Method to Define Multiple Layer Patterns With a Single Exposure by E-Beam Lithography - The present disclosure provides a method that includes forming a first resist layer on a substrate; forming a second resist layer over the first resist layer; and performing an electron-beam (e-beam) lithography exposure process to the first resist layer and the second resist layer, thereby forming a first latent feature in the first resist layer and a second latent feature in the second resist layer. | 11-20-2014 |
20140342564 | Photomask With Three States For Forming Multiple Layer Patterns With A Single Exposure - The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern. | 11-20-2014 |
20140377693 | Extreme Ultraviolet Lithography Mask and Multilayer Deposition Method for Fabricating Same - A mask, method of fabricating same, and method of using same are disclosed. In an example, a mask includes a substrate and a reflective multilayer coating deposited over the substrate. The reflective multilayer coating is formed by positioning the substrate such that an angle α is formed between a normal line of the substrate and particles landing on the substrate and rotating the substrate about an axis that is parallel with a landing direction of the particles. In an example, reflective multilayer coating includes a first layer and a second layer deposited over the first layer. A phase defect region of the reflective multilayer coating includes a first deformation in the first layer at a first location, and a second deformation in the second layer at a second location, the second location laterally displaced from the first location. | 12-25-2014 |
20150037712 | Extreme Ultraviolet (EUV) Mask, Method Of Fabricating The EUV Mask And Method Of Inspecting The EUV Mask - An out-of-band (OoB) suppression layer is applied on a reflective multiplayer (ML) coating, so as to avoid the OoB reflection and to enhance the optical contrast at 13.5 nm A material having a low reflectivity at wavelength of 193-257 nm, for example, silicon carbide (SiC), is used as the OoB suppression layer. A method of fabricating an EUV mask having the OoB suppression layer and a method of inspecting an EUV mask having the OoB suppression are also provided. | 02-05-2015 |
20150064611 | Extreme Ultraviolet (Euv) Mask And Method Of Fabricating The Euv Mask - A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance. | 03-05-2015 |
20150072271 | Extreme Ultraviolet Lithography Process and Mask - A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. An EUVL process includes receiving a mask pair having a same pattern. The mask pair includes an extreme ultraviolet (EUV) mask and a low EUV reflectivity mask. A first exposure process is performed by using the EUV mask to expose a substrate. A second exposure process is performed by using the low EUV reflectivity mask to expose the same substrate. The first exposure process is conducted according to a first exposure dose matrix and the second exposure process is conducted according to a second exposure dose matrix. | 03-12-2015 |
Tai-Xing Yu, Hsinchu TW
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20080287191 | Method and System for Computing Online/Offline Multimedia Data - A method and system for processing online/offline multimedia data are disclosed. The system comprises a remote mainframe, a local host and a portable apparatus. When the portable apparatus is electrically connected with the remote mainframe and the local host, the portable apparatus can immediately exchange multimedia data exchange with the remote mainframe and the local host. When the portable apparatus is not electrically connected with the remote mainframe and the local host, the portable apparatus can independently process the multimedia data previously received from the remote mainframe and the local host; also the portable apparatus can update the multimedia data with the remote mainframe and the local host when the portable apparatus is electrically reconnected with the remote mainframe and the local host. With the system configuration, the present invention features online/offline multimedia-data processing capabilities. | 11-20-2008 |
Teng-Yi Yu, Hsinchu TW
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20110242309 | MULTI-LENS MONITORING SYSTEM FOR BED ELEVATION AROUND A PIER - The present invention relates to a multi-lens monitoring system for bed elevation around a pier according to the present invention comprises a container, a holder, a plurality of photographing units, and a processing module. The container is disposed on the pier; the holder is disposed inside the container; and the plurality of photographing units are disposed on the holder for photographing the bed under water and producing a monitoring image. The processing module is used for activating one of the plurality of photographing units for photographing the bed under water. The processing module also analyzes the monitoring image, gives the elevation variation of the bed, and transmits the elevation variation of the bed to a remote monitoring unit for real-timely monitoring and recording. During the monitoring process, the processing module will change activating one of the plurality of photographing units according to the monitoring image, and hence the electrical power can be saved. | 10-06-2011 |
20110255735 | PROBE MONITORING SYSTEM FOR RIVERBED ELEVATION MONITORING AT BRIDGE PIERS - A probe monitoring system for riverbed elevation monitoring at bridge piers is revealed. The system includes a housing, a measuring rod, a moving member, a control module, a photographic unit and a sensing unit. The housing is fixed on the pier. Both the moving member for driving the measuring rod and the control module for control of the moving member are mounted in the housing. When the control module drives the measuring rod to move downward and the sensing unit on the bottom of the measuring rod approaches the riverbed, a sensing signal is sent to the control module. Thus the moving member stops moving the measuring rod and the photographic unit takes pictures of the measuring rod to generate an image. Then the riverbed elevation is obtained according to the image or the movement of the moving member and is sent to a remote monitor unit for real-time monitoring. | 10-20-2011 |
20120127300 | TELESCOPIC PROBE MONITORING SYSTEM FOR RIVERBEDELEVATION MONITORING AT BRIDGE PIERS - A telescopic probe monitoring system for riverbed elevation monitoring at a bridge pier is revealed. The system includes a measurement module for measuring riverbed elevation under water and a control module. The measurement module includes a housing, a multi-layer tube, a driving member with scales, a photographic unit for capturing images, and a sensing unit. The control module controls the driving member to extend the multi-layer tube. Thus the sensing unit on the bottom of the multi-layer tube contacts the riverbed and then sends a sensing signal to the control module for stopping pushing the multi-layer tube and controlling the photographic unit to capture images of the driving member. According to the images and movement of the measurement module, the control module learns the riverbed elevation and sends the riverbed elevation to a remote monitor unit for real-time monitoring of the riverbed elevation. | 05-24-2012 |
Ting-Fa Yu, Hsinchu TW
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20110311010 | DEVICE AND METHOD FOR NRZ CDR CALIBRATION - The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal. | 12-22-2011 |
Tsai-Chuan Yu, Hsinchu TW
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20080237855 | Ball grid array package and its substrate - A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities. | 10-02-2008 |
20090243099 | WINDOW TYPE BGA SEMICONDUCTOR PACKAGE AND ITS SUBSTRATE - A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections. | 10-01-2009 |
Tsung-Hsing Yu, Hsinchu TW
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20120119298 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°. | 05-17-2012 |
20150044847 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°. | 02-12-2015 |
Tsung-Lin Yu, Hsinchu TW
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20110156067 | LIGHT EMITTING MODULE AND ILLUMINATION DEVICE WITH THE SAME - A light emitting module includes a substrate, a conductive layer, a first light emitter, a second light emitter and a protection layer. The substrate has a first surface and a second surface on opposite sides of the substrate. The conductive layer is configured in the substrate. The first light emitter is disposed on the first surface and connected with the conductive layer. The second light emitter is disposed on the second surface and connected with the conductive layer. The protection layer covers the first light emitter and the second light emitter. | 06-30-2011 |
Tsung-Yi Yu, Hsinchu TW
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20120235702 | SPLIT GATE STRUCTURE AND METHOD OF USING SAME - A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB. | 09-20-2012 |
Tzu-Chi Yu, Hsinchu TW
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20100216244 | Microfluidic Chip and Method Using the Same - Disclosed is a microfluidic chip and method using the same. The microfluidic chip comprises a substrate having a surface, and at least a tissue culture area formed on the surface of the substrate. The tissue culture area has a microfluidic channel formed by a plurality of connected geometrical structures (nozzle-type channels) having a predetermined depth. The microfluidic channel has an inlet and an outlet, which are at two ends of the microfluidic channel, for medium inputting and outputting, respectively. Additionally, at least an air-exchange hole is formed on the bottom of the microfluidic channel. By using the microfluidic chip for tissue culture, lateral flow speed and stress can be decreased, so as to prolong survival time of tissues (e.g. liver tissues). | 08-26-2010 |
Tzung-Wei Yu, Hsinchu TW
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20140021473 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a gate, an oxide channel layer, a gate insulating layer, a source, a drain and a dielectric stacked layer. The oxide channel layer is stacked over the gate, with the gate insulting layer disposed therebetween. The source and the drain are disposed on a side of the oxide channel layer and in parallel to each other. A portion of the oxide channel layer is exposed between the source and the drain. The dielectric stacked layer is disposed on the substrate and includes plural of first inorganic dielectric layers with a first refraction index and plural of second inorganic dielectric layers with a second refraction index that are stacked alternately. At least one of the first inorganic dielectric layers directly covers the source, the drain and the portion of the oxide channel layer. The first refraction index is smaller than the second refraction index. | 01-23-2014 |
20140070216 | THIN FILM TRANSISTOR - A thin film transistor (TFT) is provided, which includes a substrate, a first gate layer, an insulation layer, a first source/drain layer, a second source/drain layer, a semiconductor layer, a passivation layer and a second gate layer. The first gate layer is disposed on the substrate. The insulation layer is disposed on the first gate layer. The first source/drain layer is disposed on the insulation layer. The second source/drain layer is disposed on the insulation layer. The semiconductor layer is disposed on the insulation layer and covers the first source/drain layer and the second source/drain layer. The passivation layer is disposed on the insulation layer and covers the semiconductor layer. The second gate layer is disposed on the passivation layer and contacts the first gate layer through a via so that the two gate layers keep a same voltage level. | 03-13-2014 |
20140110700 | THIN FILM TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor (TFT) structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface which is constituted by a plurality of grains separated from one another. An indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer. | 04-24-2014 |
20140183521 | THIN FILM TRANSISTOR STRUCTURE - A thin film transistor structure including a substrate, a gate, an oxide semiconductor layer, a gate insulation layer, a source, a drain, a silicon-containing light absorption layer and an insulation layer is provided. The gate insulation layer is disposed between the oxide semiconductor layer and the gate. The oxide semiconductor layer and the gate are stacked in a thickness direction. The source and the drain contact the oxide semiconductor layer. A portion of the oxide semiconductor layer without contacting the source and the drain defines a channel region located between the source and the drain. The oxide semiconductor layer is located between the substrate and the silicon-containing light absorption layer. The silicon-containing light absorption layer has a band gap smaller than 2.5 eV. The insulation layer is disposed between the oxide semiconductor layer and the silicon-containing light absorption layer, and in contact with the silicon-containing light absorption layer. | 07-03-2014 |
20140267995 | PIXEL STRUCTURE - A pixel structure disposed on a substrate is provided. The pixel structure includes an active device, a first electrode, a second electrode and an alignment layer. The active device is disposed on the substrate. The first electrode is disposed on the substrate and has a plurality of slits. A thickness of the first electrode is from 20 Å to 100 Å. The second electrode is disposed on the substrate and electrically independent from the first electrode. A portion of the area of the second electrode is located inside the first slits. One of the first electrode and the second electrode is electrically connected to the active device. The alignment layer covers at least the first electrode and the first slits. | 09-18-2014 |
20140361970 | REFLECTIVE DISPLAY DEVICE AND DRIVING METHOD THEREOF - A reflective display device includes a drive array substrate, an electrophoretic display film, a reflective optical film and a light source module. The electrophoretic display film is disposed on the drive array substrate and includes a plurality of display mediums. The reflective optical film is disposed on the electrophoretic display film. The light source module is disposed beside the reflective optical film. A light emitting from the light source module is reflected to the electrophoretic display film by the reflective optical film. The light source module includes a plurality of first-color light sources, a plurality of second-color light sources and a plurality of third-color light sources which are switched on in sequence. The reflective display device is in a color display mode when the light source module is turned on. The reflective display device is in a monochrome display mode when the light source module is turned off. | 12-11-2014 |
Wan-Jhang Yu, Hsinchu TW
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20110007367 | CALIBRATING DEVICE, MAPPING METHOD AND COMPENSATION METHOD USING THE SAME - A calibrating device including a pixel unit array and a pattern is provided. The pixel unit array comprises parallel warp lines and parallel weft lines. Each warp line crosses each weft line to define pixel units all over the pixel unit array. The pattern comprises some pixel units having a gray level different from a gray level of remainder pixel units in the pixel unit array. The pattern comprises spaced bars parallel to one another and not parallel to the warp lines and the weft lines. A characteristic of the pattern is utilized to define target pixel units and comparison pixel units, and the comparison procedure is implemented with the characteristic of the pattern. Positions and gap sizes of gaps between image sensors are mapped out by comparing the target pixel units with the comparison pixel units. The quality of a scanned image is improved with compensation for the gaps. | 01-13-2011 |
Wei-Sheng Yu, Hsinchu TW
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20090142864 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A method for manufacturing a thin film transistor (TFT) array substrate needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain. Thus, the difficulty of the manufacturing process is effectively reduced. | 06-04-2009 |
20090173943 | ACTIVE MATRIX ARRAY STRUCTURE AND MANUFACTURING MEHTOD THEREOF - An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer. | 07-09-2009 |
20100213464 | ACTIVE MATRIX ARRAY STRUCTURE - An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer. | 08-26-2010 |
Wen-Chein Yu, Hsinchu TW
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20100213440 | Silicon-Quantum-Dot Semiconductor Near-Infrared Photodetector - A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response. | 08-26-2010 |
Wen-Hao Yu, Hsinchu TW
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20110133836 | CLASS-D AMPLIFIER - Class D amplifier is provided. The class D amplifier includes at least a block; each block includes an input circuit, an integrator, a comparator, a driving circuit and two feedback circuits. The input circuit receives a digital input to provide a differential pair of a positive and a negative input signals. The integrator receives the positive and negative input signals and a pair of positive and negative feedback signals for providing a positive error signal according to the positive input signal and the negative feedback signal, and providing a negative error signal according to the negative input signal and the positive feedback signal. The comparator compares between the positive and the negative error signals such that the driving circuit generates a driving output signal according to comparison result. The two feedback circuits respectively providing said positive and negative feedback signals according to the driving output signal. | 06-09-2011 |
Wen-Huai Yu, Hsinchu TW
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20110142730 | Crystalline Silicon Formation Apparatus - In a crystalline silicon formation apparatus, a quick cooling method is applied to the bottom of a crucible to control a growth orientation of a polycrystalline silicon grain, such that the crystal grain forms twin boundary, and the twin boundary is a symmetric grain boundary, and the crystal grain is solidified and grown upward in unidirection to form a complete polycrystalline silicon, such that defects or impurities will not form in the polycrystalline silicon easily. | 06-16-2011 |
20130095027 | CRYSTALLINE SILICON INGOT AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm. | 04-18-2013 |
20130095028 | CRYSTALLINE SILICON INGOT AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of manufacturing the same are provided. Using a crystalline silicon seed layer, the crystalline silicon ingot is formed by a directional solidification process. The crystalline silicon seed layer is formed of multiple primary monocrystalline silicon seeds and multiple secondary monocrystalline silicon seeds. Each of the primary monocrystalline silicon seeds has a first crystal orientation different from (100). Each of the secondary monocrystalline silicon seeds has a second crystal orientation different from the first crystal orientation. Each of the primary monocrystalline silicon seeds is adjacent to at least one of the secondary monocrystalline silicon seeds, and separate from the others of the primary monocrystalline silicon seeds. | 04-18-2013 |
20130133569 | Crystal Growth Device - A crystal growth device includes a crucible and a heater setting. The crucible has a bottom and a top opening. The heater setting surrounds the crucible and is movable relative to the crucible along a top-bottom direction of the crucible and between first and second positions. The heater setting includes a first temperature heating zone and a second temperature heating zone higher in temperature than the first temperature heating zone. The heater setting is in the first position when the crucible is in the second temperature heating zone and in the second position when the crucible is in the first temperature heating zone. | 05-30-2013 |
20130136918 | CRYSTALLINE SILICON INGOT INCLUDING NUCLEATION PROMOTION LAYER AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm. | 05-30-2013 |
20140127496 | CRYSTALLINE SILICON INGOT INCLUDING NUCLEATION PROMOTION LAYER AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm. | 05-08-2014 |
20140186631 | SEED USED FOR CRYSTALLINE SILICON INGOT CASTING - The invention discloses a seed used for crystalline silicon ingot casting. A seed according to a preferred embodiment of the invention includes a crystal and an impurity diffusion-resistant layer. The crystal is constituted by at least one grain. The impurity diffusion-resistant layer is formed to overlay an outer surface of the crystal. A crystalline silicon ingot fabricated by use of the seed of the invention has significantly reduced red zone and yellow zone. | 07-03-2014 |
Xiong-Fei Yu, Hsinchu TW
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20110081774 | METHODS FOR A GATE REPLACEMENT PROCESS - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 04-07-2011 |
20110143529 | METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE - The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench. | 06-16-2011 |
20110256682 | Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device - A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O | 10-20-2011 |
20110256731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER - A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer. | 10-20-2011 |
20120261758 | METHOD OF FABRICATING A GATE DIELECTRIC LAYER - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate having a first active region; a first gate structure over the first active region, wherein the first gate structure comprises a first interfacial layer having a convex top surface; a first high-k dielectric over the first interfacial layer; and a first gate electrode over the first high-k dielectric. | 10-18-2012 |
20120264281 | METHOD OF FABRICATING A PLURALITY OF GATE STRUCTURES - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode. | 10-18-2012 |
20130017678 | METHODS OF ANNEAL AFTER DEPOSITION OF GATE LAYERSAANM TSAI; Chun HsiungAACI Xinpu TownshipAACO TWAAGP TSAI; Chun Hsiung Xinpu Township TWAANM YU; Xiong-FeiAACI HsinchuAACO TWAAGP YU; Xiong-Fei Hsinchu TWAANM HUANG; Yu-LienAACI Jhubei CityAACO TWAAGP HUANG; Yu-Lien Jhubei City TWAANM LIN; Da-WenAACI Hsinchu CityAACO TWAAGP LIN; Da-Wen Hsinchu City TW - Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer. | 01-17-2013 |
20130026637 | METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR - An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10. | 01-31-2013 |
20130032900 | BUFFER LAYER AND METHOD OF FORMING BUFFER LAYER - Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer. | 02-07-2013 |
20130056836 | Techniques Providing Metal Gate Devices with Multiple Barrier Layers - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers. | 03-07-2013 |
20130149821 | Methods for a Gate Replacement Process - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 06-13-2013 |
20140004694 | METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR | 01-02-2014 |
20140291777 | BUFFER LAYER ON SEMICONDUCTOR DEVICES - A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon. | 10-02-2014 |
20140335685 | METHODS OF ANNEALING AFTER DEPOSITION OF GATE LAYERS - A method of fabricating a gate structure includes depositing a high dielectric constant (high-k) dielectric layer over a substrate. The method further includes performing a multi-stage preheat high-temperature anneal. Performing the multi-stage preheat high-temperature anneal includes performing a first stage preheat at a temperature in a range from about 400° C. to about 600° C., performing a second stage preheat at a temperature in a range from about 700° C. to about 900° C., and performing a high temperature anneal at a peak temperature in a range from 875° C. to about 1200° C. | 11-13-2014 |
20140363962 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of making a semiconductor device includes forming a high-k dielectric layer over a substrate; and forming a titanium nitride layer over the high-k dielectric layer. The method further includes performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer. The method further includes annealing the semiconductor device to form a TiSiON layer over a remaining portion of the titanium nitride layer. | 12-11-2014 |
20150017796 | TECHNIQUES PROVIDING METAL GATE DEVICESWITH MULTIPLE BARRIER LAYERS - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers. | 01-15-2015 |
Yeh-Wei Yu, Hsinchu TW
Patent application number | Description | Published |
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20090303560 | Spatial Light Modulator - A spatial light modulator applied to the collinear volume holographic storage system uses a hollow phase modulator to modulate the surrounding portion of an incident light to be a reference light, and the center portion of the incident light is modulated by a strength modulator to be a signal light. Thus, the spatial light modulator can enhance the convergence of the point spread function of the system. | 12-10-2009 |
20100259803 | COLLINEAR VOLUME HOLOGRAPHIC OPTICAL STORAGE SYSTEM AND INFORMATION STORAGE STRUCTURE THEREOF - A collinear volume holographic optical storage system records a plurality pages of holographic data on the storage material, where the intensity distribution of the saved recorded holographic data of each page is in a “+” format. It is possible to incur the inter-page cross talk between two adjacent pages of holographic data along the storage track or between two adjacent storage tracks. An rotation angle between the direction of the distribution of the volume grating and the direction of the storage track can be used to increase the descendent of data storage intensity along storage track, so the effect of the inter-page cross talk is decreased; or the distance between reading centers of two pages of holographic data is shorten to increase the storage density of the storage material. | 10-14-2010 |
Yi-Jen Yu, Hsinchu TW
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20080287191 | Method and System for Computing Online/Offline Multimedia Data - A method and system for processing online/offline multimedia data are disclosed. The system comprises a remote mainframe, a local host and a portable apparatus. When the portable apparatus is electrically connected with the remote mainframe and the local host, the portable apparatus can immediately exchange multimedia data exchange with the remote mainframe and the local host. When the portable apparatus is not electrically connected with the remote mainframe and the local host, the portable apparatus can independently process the multimedia data previously received from the remote mainframe and the local host; also the portable apparatus can update the multimedia data with the remote mainframe and the local host when the portable apparatus is electrically reconnected with the remote mainframe and the local host. With the system configuration, the present invention features online/offline multimedia-data processing capabilities. | 11-20-2008 |
Yu-Ping Yu, Hsinchu TW
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20130155928 | POWER MANAGEMENT IN A MOBILE COMMUNICATION SYSTEM - A device in a base station of a mobile communication system for power management can include a storage device to store a group of parameter sets associated with a user equipment (UE) of the mobile communication system. The device can include a processor to calculate a corresponding objective function associated with each entity of the group of parameter sets. The processor can be configured to select an entity of the group of parameter sets based on the corresponding objective function, and the selected entity of the group of parameter sets facilitates the power management for the UE. | 06-20-2013 |