Patent application number | Description | Published |
20110248949 | EQUALIZING PARASITIC CAPACITANCE EFFECTS IN TOUCH SCREENS - Reduction of the effects of differences in parasitic capacitances in touch screens is provided. A touch screen can include multiple display pixels with stackups that each include a first element and a second element. For example, the first element can be a common electrode, and the second element can be a data line. The display pixels can include a first display pixel including a third element connected to the first element, and the third element can contribute to a first parasitic capacitance between the first and second elements of the first display pixel, for example, by overlapping with the second element. The touch screen can also include a second display pixel lacking the third element. The second display pixel can include a second parasitic capacitance between the first and second elements of the second display pixel. The first and second parasitic capacitances can be substantially equal, for example. | 10-13-2011 |
20110267283 | Kickback Voltage Equalization - Scanning gate lines in a gate driver system of a touch screen is provided. The gate driver system can include gate lines connected to display pixel transistors, a display driver that can generate first and second gate clock signals including first and second voltage transitions, respectively, and a gate drivers that can receive the first and second gate clock signals via gate clock lines and that can apply gate line signals, based on the gate clock signals, to the gate lines. A first voltage change generated in a common electrode line of the touch screen by the first voltage transition can be reduced by a second voltage change generated in the common electrode by the second voltage transition. | 11-03-2011 |
20120154699 | DISPLAYS WITH MINIMIZED CROSSTALK - Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity. | 06-21-2012 |
20120162121 | SLEW RATE AND SHUNTING CONTROL SEPARATION - Setting a slew rate, e.g., a rising time or a falling time, of a scanning signal can be performed with a first operation, and a shunting resistance of the scanning line can be set with a second operation. A scanning system that scans a display screen, a touch screen, etc., can set a desired slew rate during a first period of time and can set a desired shunting resistance during a second period of time. A gate line system can sequentially scan gate lines to display an image during a display phase of a touch screen. The gate line system can, for example, increase the falling times of gate line signals. After the falling gate line signal has stabilized, for example, the gate line system can decrease the shunting resistance of the gate line. | 06-28-2012 |
20120280957 | DISPLAY EDGE SEAL IMPROVEMENT - Embodiments of the present disclosure relate to liquid crystal displays (LCDs) and electronic devices incorporating LCDs having an organic passivation layer positioned between edge-sealed two substrates. Specifically, embodiments of the present disclosure employ lithographic techniques (e.g., a half-tone mask, diffractive exposure mask, etc.) to remove or not deposit a portion of the organic passivation layer near the edges of the substrates prior to sealing the substrates along these edges. As described herein, this reduction in the thickness of the organic layer near the edges of the device may improve the strength of the edge seal due to reduced strain in the organic layer. | 11-08-2012 |
20120293485 | GATE SIGNAL ADJUSTMENT CIRCUIT - A gate signal adjustment circuit for a display is disclosed. The gate signal adjustment circuit can adjust a transition time of a gate signal used to drive data displaying. The adjustment can be to either speed up or slow down the transition time according to the requirements of the display. In an example, the gate signal adjustment circuit can include multiple transistors, where a first set of the transistors outputs the gate signal and a second set of the transistors outputs an adjustment to the gate signal. The second set of transistors can be the same or different sizes depending on the desirable number of adjustment options. The circuit can also include a control line coupled to the second set of transistors to control the adjustment output. Gate signal adjustment can reduce crosstalk in the display. | 11-22-2012 |
20120299983 | WRITING DATA TO SUB-PIXELS USING DIFFERENT WRITE SEQUENCES - With respect to liquid crystal display inversion schemes, a large change in voltage on a data line can affect the voltages on adjacent data lines due to capacitive coupling between data lines. The resulting change in voltage on these adjacent data lines can give rise to visual artifacts in the data lines' corresponding sub-pixels. Various embodiments of the present disclosure serve to prevent or reduce persisting visual artifacts by offsetting their effects or by distributing their presence among different colored sub-pixels. In some embodiments, this may be accomplished by using different write sequences during the update of a row of pixels. | 11-29-2012 |
20120313881 | DISPLAY SCREEN SHIELD LINE SYSTEM - Electrical shield line systems are provided for openings in common electrodes near data lines of display and touch screens. Some displays, including touch screens, can include multiple common electrodes (Vcom) that can have openings between individual Vcoms. Some display screens can have an open slit between two adjacent edges of Vcom. Openings in Vcom can allow an electric field to extend from a data line through the Vcom layer. A shield can be disposed over the Vcom opening to help reduce or eliminate an electric field from affecting a pixel material, such as liquid crystal. The shield can be connected to a potential such that electric field is generated substantially between the shield and the data line to reduce or eliminate electric fields reaching the liquid crystal. | 12-13-2012 |
20130052971 | INTERFERENCE REDUCTION SYSTEMS AND METHODS - The antenna on hand held devices, such as the iPhone or iPad, can be subject to interference from other circuitry on the device. Such interference may come from high frequency switching of nearby display circuitry, such as de-multiplexors or other circuits. To address this issue, the switching rates may be slowed in certain circuits by adding resistance and/or capacitance, thus raising the RC time constant and slowing the switching times to reduce the high frequency components. Alternatively or in addition to, an EMI shield can be placed over some or all of the display driving circuitry to shield the antenna from high frequency interference. | 02-28-2013 |
20130141343 | COMMON ELECTRODE CONNECTIONS IN INTEGRATED TOUCH SCREENS - Common electrodes (Vcom) of integrated touch screens can be segmented into electrically isolated Vcom portions that can be operated as drive lines and/or sense lines of a touch sensing system. The touch screen can include high-resistivity connections between Vcom portions. The resistivity of the high-resistivity connections can be high enough so that touch sensing and image display can be performed by the touch screen, and the high-resistivity connections can provide an added functionality by allowing a charge build up on one of the Vcom portions to be spread to other Vcom portions and/or discharged from system by allowing charge to leak through the high-resistivity connections. In this way, for example, visual artifacts that result from charge build up on a Vcom portion can be reduced or eliminated. | 06-06-2013 |
20130147774 | DISPLAYS WITH MINIMIZED CROSSTALK - Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity. | 06-13-2013 |
20130271684 | DEVICES AND METHODS FOR REDUCING THE SIZE OF DISPLAY PANEL ROUTINGS - Disclosed embodiments relate to signal routings for use in a display device. The display device may include a liquid crystal display (LCD) panel having multiple pixels arranged in rows and columns. Each of the pixels includes a pixel electrode and a thin-film transistor (TFT). The LCD may include a conductive signal routing portion having a first metallic layer, a second metallic layer formed directly on the first metallic layer, and a third metallic layer formed directly on the second metallic layer. The first metallic layer may include a contact terminal. The second metallic layer when combined with the third metallic layers may decrease the resistance of the third metallic layer. | 10-17-2013 |
20130300681 | LOW COMPLEXITY GATE LINE DRIVER CIRCUITRY - Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line, and the latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Other embodiments are also described and claimed. | 11-14-2013 |
20130328053 | Thin Film Transistor with Increased Doping Regions - A transistor that may be used in electronic displays to selectively activate one or more pixels. The transistor includes a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer includes an extension portion that extends a distance past the metal layer, and at least three lightly doped regions positioned in the silicon layer. The at least three lightly doped regions have a lower concentration of doping atoms than other portions of the silicon layer forming the transistor. | 12-12-2013 |
20130329171 | DEVICES AND METHODS FOR SHIELDING DISPLAYS FROM ELECTROSTATIC DISCHARGE - Methods and devices for shielding displays from electrostatic discharge (ESD) are provided. In one example, a display of an electronic device may include a high resistivity shielding layer configured to protect electrical components from static charges. The display may also include a conductive layer electrically coupled to the high resistivity shielding layer and configured to decrease a discharge time of static charges from the high resistivity shielding layer. The display may include a grounding layer and a conductor electrically coupled between the conductive layer and the grounding layer to direct static charges from the conductive layer to the grounding layer. | 12-12-2013 |
20140043552 | Display with Multilayer and Embedded Signal Lines - A display may have a thin-film-transistor layer with a substrate layer. A layer of dielectric may be formed on the substrate layer and may have an upper surface and a lower surface. The thin-film-transistor layer may include an array of display pixels. Data lines and gate lines may provide signals to the display pixels. Gate driver circuitry in an inactive peripheral portion of the display may include a gate driver circuit for each gate line. The gate driver circuits may include thin-film transistors that are formed on the upper surface of the layer of dielectric. Signal lines such as a gate low line, a gate routing line coupled between the gate driver circuits, and a common electrode line may be formed from two or more layers of metal to reduce their widths or may be embedded within the dielectric layer between the upper and lower surfaces under the thin-film transistors. | 02-13-2014 |
20140061656 | Two Doping Regions in Lightly Doped Drain for Thin Film Transistors and Associated Doping Processes - A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose. | 03-06-2014 |
20140070225 | Hydrogenation and Crystallization of Polycrystalline Silicon - A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer C | 03-13-2014 |
20140103349 | DIFFERENT LIGHTLY DOPED DRAIN LENGTH CONTROL FOR SELF-ALIGN LIGHT DRAIN DOPING PROCESS - A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose. | 04-17-2014 |
20140146026 | Electronic Device with Compact Gate Driver Circuitry - An electronic device display may have an array of display pixels that are controlled using a grid of data lines and gate lines. The display may include compact gate driver circuits that perform gate driver operations to drive corresponding gate lines. Each compact gate driver circuit may include a first driver stage and a second driver stage. The first driver stage may receive a start pulse signal and produce a control signal. The control signal may be stored by a capacitor to identify a control state of the gate driver circuit. The second driver stage may receive the control signal, a clock signal, and a corresponding inverted clock signal and drive the corresponding gate line based on the received signals. The second driver stage may include pass transistor circuitry that passes the clock signal to the corresponding gate line and may include short circuit protection circuitry. | 05-29-2014 |
20140232626 | DISPLAY PANEL SOURCE LINE DRIVING CIRCUITRY - An electronic display system has a light transmissive panel, a region of display elements on the panel, and source lines coupled to the display elements. A demultiplexor circuit has multiple groups of pass gates. Each pass gate has a pair of complimentary on-panel transistors, and the signal outputs of each group are connected to a respective group of the source lines. A display driver integrated circuit (IC) receives video data and timing control signals. A signal input of each group of pass gates is connected to a respective output pin of the driver IC. The display driver IC provides digital timing control signals to control the pass gates of the demultiplexor circuit. Other embodiments are also described. | 08-21-2014 |
20140232955 | Display Circuitry with Reduced Pixel Parasitic Capacitor Coupling - A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. Each display pixel in the TFT layer may include first and second TFTs coupled in series between a data line and a storage capacitor. The first TFT may have a gate that is coupled to a gate line. The second TFT may have a gate that is coupled to a control line that is different than the gate line. A global enable signal may be provided on the control line, where the enable signal is asserted during display intervals and is deasserted during touch intervals. The second TFT may be formed using a top-gate TFT or a bottom-gate TFT arrangement. | 08-21-2014 |
20140247239 | DISPLAY INTEGRATED PRESSURE SENSOR - A touch sensitive device that can detect the amount of pressure being applied to a touch screen from a user or other external object is provided. A spacer of the touch screen can be coated with a layer of conductive material and the change in capacitance between the spacer and various circuit elements of the touch screen can be measured. The change in capacitance can be correlated to the amount of pressure being applied to the touch screen, thus providing a method to determine the pressure being applied. During operation of the device, the system can time multiplex touch, display and pressure sensing operations so as to take advantage of an integrated touch and display architecture. | 09-04-2014 |
20140327632 | Displays with Integrated Touch and Improved Image Pixel Aperture - A display may be provided with integral touch functionality. The display may include a common electrode layer having row electrodes arranged in rows and column electrodes interposed between the row electrodes of each row. The row electrodes may be electrically coupled by conductive paths. The row and column electrodes may be coupled to touch sensor circuitry that uses the row and column electrodes to detect touch events. Each electrode of the common electrode layer may cover a respective portion of an array of pixels. Each pixel of the display may have a respective aperture. The conductive paths that electrically couple row electrodes of the common electrode layer may cover or otherwise block some light from passing through pixels, resulting in reduced apertures. Dummy structures may be provided for other pixels that modify the apertures of the other pixels to match the reduced apertures associated with the conductive paths. | 11-06-2014 |
20150015559 | LIQUID CRYSTAL DISPLAY USING DEPLETION-MODE TRANSISTORS - Methods and devices employing charge removal circuitry are provided to reduce or eliminate artifacts due to a bias voltage remaining on an electronic display after the display is turned off. In one example, a method may include connecting a pixel electrode of a display to ground through charge removal circuitry while the display is off (e.g., using depletion-mode transistors that are active when gates of the depletion-mode transistors are provided a ground voltage). When a corresponding common electrode is also connected to ground, a voltage difference between the pixel electrode and common electrode may be reduced or eliminated, preventing a bias voltage from causing display artifacts in the pixel. | 01-15-2015 |
20150054799 | Display Driver Circuitry For Liquid Crystal Displays With Semiconducting-Oxide Thin-Film Transistors - An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure. | 02-26-2015 |
20150055047 | Liquid Crystal Displays with Oxide-Based Thin-Film Transistors - An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure. | 02-26-2015 |
Patent application number | Description | Published |
20080308416 | SPUTTERING TARGET HAVING INCREASED LIFE AND SPUTTERING UNIFORMITY - A sputtering target for a sputtering chamber comprises a backing plate with a sputtering plate mounted thereon. In one version, the backing plate comprises a circular plate having a front surface comprising an annular groove. The sputtering plate comprises a disk comprising a sputtering surface and a backside surface having a circular ridge that is shaped and sized to fit into the annular groove of the backing plate. | 12-18-2008 |
20090053426 | COBALT DEPOSITION ON BARRIER SURFACES - Embodiments of the invention provide processes for depositing a cobalt layer on a barrier layer and subsequently depositing a conductive material, such as copper or a copper alloy, thereon. In one embodiment, a method for depositing materials on a substrate surface is provided which includes forming a barrier layer on a substrate, exposing the substrate to dicobalt hexacarbonyl butylacetylene (CCTBA) and hydrogen to form a cobalt layer on the barrier layer during a vapor deposition process (e.g., CVD or ALD), and depositing a conductive material over the cobalt layer. In some examples, the barrier layer and/or the cobalt layer may be exposed to a gas or a reagent during a treatment process, such as a thermal process, an in situ plasma process, or a remote plasma process. | 02-26-2009 |
20090087983 | ALUMINUM CONTACT INTEGRATION ON COBALT SILICIDE JUNCTION - Embodiments herein provide methods for forming an aluminum contact on a cobalt silicide junction. In one embodiment, a method for forming materials on a substrate is provided which includes forming a cobalt silicide layer on a silicon-containing surface of the substrate during a silicidation process, forming a fluorinated sublimation film on the cobalt silicide layer during a plasma process, heating the substrate to a sublimation temperature to remove the fluorinated sublimation film, depositing a titanium-containing nucleation layer over the cobalt silicide layer, and depositing an aluminum-containing material over the titanium-containing nucleation layer. In one example, the method further provides forming the cobalt silicide layer by depositing a cobalt-containing layer on the silicon-containing surface, heating the substrate during a rapid thermal annealing (RTA) process, etching away any remaining portions of the cobalt-containing layer from the substrate, and subsequently heating the substrate during another RTA process. | 04-02-2009 |
20100003406 | APPARATUSES AND METHODS FOR ATOMIC LAYER DEPOSITION - Embodiments of the invention provide apparatuses and methods for atomic layer deposition (ALD), such as plasma-enhanced ALD (PE-ALD). In some embodiments, a PE-ALD chamber is provided which includes a chamber lid assembly coupled with a chamber body having a substrate support therein. In one embodiment, the chamber lid assembly has an inlet manifold assembly containing an annular channel encompassing a centralized channel, wherein the centralized channel extends through the inlet manifold assembly, and the inlet manifold assembly further contains injection holes extending from the annular channel, through a sidewall of the centralized channel, and to the centralized channel. The chamber lid assembly further contains a showerhead assembly disposed below the inlet manifold assembly, a water box disposed between the inlet manifold assembly and the showerhead assembly, and a remote plasma system (RPS) disposed above and coupled with the inlet manifold assembly, and in fluid communication with the centralized channel. | 01-07-2010 |
20100102417 | VAPOR DEPOSITION METHOD FOR TERNARY COMPOUNDS - Embodiments provide a method for depositing or forming titanium aluminum nitride materials during a vapor deposition process, such as atomic layer deposition (ALD) or plasma-enhanced ALD (PE-ALD). In some embodiments, a titanium aluminum nitride material is formed by sequentially exposing a substrate to a titanium precursor and a nitrogen plasma to form a titanium nitride layer, exposing the titanium nitride layer to a plasma treatment process, and exposing the titanium nitride layer to an aluminum precursor while depositing an aluminum layer thereon. The process may be repeated multiple times to deposit a plurality of titanium nitride and aluminum layers. Subsequently, the substrate may be annealed to form the titanium aluminum nitride material from the plurality of layers. In other embodiments, the titanium aluminum nitride material may be formed by sequentially exposing the substrate to the nitrogen plasma and a deposition gas which contains the titanium and aluminum precursors. | 04-29-2010 |
20110124192 | PROCESS FOR FORMING COBALT-CONTAINING MATERIALS - Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material. | 05-26-2011 |
20110233778 | FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer without depositing a tungsten nucleation layer on the tungsten nitride layer as a growth site for tungsten. | 09-29-2011 |
20110263115 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for processing a substrate is provided which includes depositing a dielectric material having a dielectric constant greater than 10, forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 10-27-2011 |
20110298062 | METAL GATE STRUCTURES AND METHODS FOR FORMING THEREOF - Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode. | 12-08-2011 |
20110312148 | CHEMICAL VAPOR DEPOSITION OF RUTHENIUM FILMS CONTAINING OXYGEN OR CARBON - Methods for depositing ruthenium-containing films are provided herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing film to an oxygen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the oxygen-containing gas exposed ruthenium-containing film may be annealed in a hydrogen-containing gas to remove at least some oxygen from the ruthenium-containing film. In some embodiments, the deposition, exposure, and annealing may be repeated to deposit the ruthenium-containing film to a desired thickness. | 12-22-2011 |
20120000422 | APPARATUSES AND METHODS FOR ATOMIC LAYER DEPOSITION - Embodiments of the invention provide apparatuses and methods for atomic layer deposition (ALD), such as plasma-enhanced ALD (PE-ALD). In some embodiments, a PE-ALD chamber is provided which includes a chamber lid assembly coupled with a chamber body having a substrate support therein. In one embodiment, the chamber lid assembly has an inlet manifold assembly containing an annular channel encompassing a centralized channel, wherein the centralized channel extends through the inlet manifold assembly, and the inlet manifold assembly further contains injection holes extending from the annular channel, through a sidewall of the centralized channel, and to the centralized channel. The chamber lid assembly further contains a showerhead assembly disposed below the inlet manifold assembly, a water box disposed between the inlet manifold assembly and the showerhead assembly, and a remote plasma system (RPS) disposed above and coupled with the inlet manifold assembly, and in fluid communication with the centralized channel. | 01-05-2012 |
20120012465 | METHODS FOR FORMING BARRIER/SEED LAYERS FOR COPPER INTERCONNECT STRUCTURES - Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and bottom surface of the opening; and depositing a conductive material on the layer to fill the opening. In some embodiments, one of ruthenium (Ru) or cobalt (Co) is deposited on the sidewall and bottom surface of the opening. The materials may be deposited by chemical vapor deposition (CVD) or by physical vapor deposition (PVD). | 01-19-2012 |
20120141667 | METHODS FOR FORMING BARRIER/SEED LAYERS FOR COPPER INTERCONNECT STRUCTURES - Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and the bottom surface of the opening, the layer having a first surface adjacent to the sidewall and bottom surface of the opening and a second surface opposite the first surface, wherein the second surface comprises predominantly at least one of ruthenium (Ru) or cobalt (Co) and wherein a predominant quantity of manganese (Mn) in the layer is not disposed proximate the second surface; and depositing a conductive material on the layer to fill the opening. | 06-07-2012 |
20120231626 | FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer. | 09-13-2012 |
20120264291 | PROCESS FOR FORMING COBALT-CONTAINING MATERIALS - Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material. | 10-18-2012 |
20130008984 | APPARATUSES AND METHODS FOR ATOMIC LAYER DEPOSITION - Embodiments of the invention provide apparatuses and methods for atomic layer deposition (ALD), such as plasma-enhanced ALD (PE-ALD). In some embodiments, a PE-ALD chamber is provided which includes a chamber lid assembly coupled with a chamber body having a substrate support therein. In one embodiment, the chamber lid assembly has an inlet manifold assembly containing an annular channel encompassing a centralized channel, wherein the centralized channel extends through the inlet manifold assembly, and the inlet manifold assembly further contains injection holes extending from the annular channel, through a sidewall of the centralized channel, and to the centralized channel. The chamber lid assembly further contains a showerhead assembly disposed below the inlet manifold assembly, a water box disposed between the inlet manifold assembly and the showerhead assembly, and a remote plasma system (RPS) disposed above and coupled with the inlet manifold assembly, and in fluid communication with the centralized channel. | 01-10-2013 |
20130146468 | CHEMICAL VAPOR DEPOSITION (CVD) OF RUTHENIUM FILMS AND APPLICATIONS FOR SAME - Methods for depositing ruthenium-containing films are disclosed herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing layer to a hydrogen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the hydrogen-containing gas exposed ruthenium-containing film may be subsequently exposed to an oxygen-containing gas to at least one of remove at least some carbon from or add oxygen to the ruthenium-containing film. In some embodiments, the deposition and exposure to the hydrogen-containing gas and optionally, the oxygen-containing gas may be repeated to deposit the ruthenium-containing film to a desired thickness. | 06-13-2013 |
20130189840 | METHODS FOR FORMING A CONTACT METAL LAYER IN SEMICONDUCTOR DEVICES - Methods for forming a contact metal layer in a contact structure in semiconductor devices are provided in the present invention. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device includes pulsing a deposition precursor gas mixture to a surface of a substrate disposed in a metal deposition processing chamber, pulsing a purge gas mixture to an edge of the substrate, wherein the purge gas mixture includes at least a hydrogen containing gas and an inert gas, and forming a contact metal layer on the substrate from the first deposition precursor gas mixture. | 07-25-2013 |
20130260555 | METHOD OF ENABLING SEAMLESS COBALT GAP-FILL - Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved. | 10-03-2013 |
20140106083 | TUNGSTEN GROWTH MODULATION BY CONTROLLING SURFACE COMPOSITION - A method for selectively controlling deposition rate of a catalytic material during a catalytic bulk CVD deposition is disclosed herein. The method can include positioning a substrate in a processing chamber including both surface regions and gap regions, depositing a first nucleation layer comprising tungsten conformally over an exposed surface of the substrate, treating at least a portion of the first nucleation layer with activated nitrogen, wherein the activated nitrogen is deposited preferentially on the surface regions, reacting a first deposition gas comprising tungsten halide and hydrogen-containing gas to deposit a tungsten fill layer preferentially in gap regions of the substrate, reacting a nucleation gas comprising a tungsten halide to form a second nucleation layer, and reacting a second deposition gas comprising tungsten halide and a hydrogen-containing gas to deposit a tungsten field layer. | 04-17-2014 |
20140120712 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 05-01-2014 |
20140134351 | METHOD TO DEPOSIT CVD RUTHENIUM - Methods for depositing ruthenium by a PECVD process are described herein. Methods for depositing ruthenium can include positioning a substrate in a processing chamber, the substrate having a barrier layer formed thereon, heating and maintaining the substrate at a first temperature, flowing a first deposition gas into a processing chamber, the first deposition gas comprising a ruthenium containing precursor, generating a plasma from the first deposition gas to deposit a first ruthenium layer over the barrier layer, flowing a second deposition gas into the processing chamber to deposit a second ruthenium layer over the first ruthenium layer, the second deposition gas comprising a ruthenium containing precursor, depositing a copper seed layer over the second ruthenium layer and annealing the substrate at a second temperature. | 05-15-2014 |
20140326276 | COBALT REMOVAL FOR CHAMBER CLEAN OR PRE-CLEAN PROCESS - Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a semiconductor substrate processing chamber. In one implementation, a method for removing cobalt or cobalt containing deposits from one or more interior surfaces of a substrate processing chamber after processing a substrate disposed in the substrate processing chamber is provided. The method comprises forming a reactive species from the fluorine containing cleaning gas mixture, permitting the reactive species to react with the cobalt and/or the cobalt containing deposits to form cobalt fluoride in a gaseous state and purging the cobalt fluoride in gaseous state out of the substrate processing chamber. | 11-06-2014 |
20150050807 | TUNGSTEN DEPOSITION WITH TUNGSTEN HEXAFLUORIDE (WF6) ETCHBACK - Implementations described herein generally relate to methods for forming tungsten materials on substrates using vapor deposition processes. The method comprises positioning a substrate having a feature formed therein in a substrate processing chamber, depositing a first film of a bulk tungsten layer by introducing a continuous flow of a hydrogen containing gas and a tungsten halide compound to the processing chamber to deposit the first tungsten film over the feature, etching the first film of the bulk tungsten layer using a plasma treatment to remove a portion of the first film by exposing the first film to a continuous flow of the tungsten halide compound and an activated treatment gas and depositing a second film of the bulk tungsten layer by introducing a continuous flow of the hydrogen containing gas and the tungsten halide compound to the processing chamber to deposit the second tungsten film over the first tungsten film. | 02-19-2015 |
20150076110 | BORON IONIZATION FOR ALUMINUM OXIDE ETCH ENHANCEMENT - Embodiments described herein generally provide a method for performing a semiconductor precleaning process. More specifically, embodiments provided herein relate to boron ionization for aluminum oxide etch enhancement. A process for removing native oxide from aluminum may utilize ionized boron alone or in combination with a halogen plasma. The ionized boron may provide improved aluminum oxide etching properties while being highly selective for native oxides more generally. | 03-19-2015 |
20150093891 | METHOD OF ENABLING SEAMLESS COBALT GAP-FILL - Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved. | 04-02-2015 |