Patent application number | Description | Published |
20090072298 | Semiconductor device and method of manufacturing the same - An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer. | 03-19-2009 |
20090212340 | FLASH MEMORY DEVICES - A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region. | 08-27-2009 |
20090315099 | METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased. | 12-24-2009 |
20100133604 | Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern. | 06-03-2010 |
20110084329 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer. | 04-14-2011 |
20110117713 | METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased. | 05-19-2011 |
20110117722 | Semiconductor Device With Charge Storage Pattern And Method For Fabricating The Same - A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns. | 05-19-2011 |
20110119564 | FLASH MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data. | 05-19-2011 |
20110260237 | VERTICAL MEMORY DEVICES WITH QUANTUM-DOT CHARGE STORAGE CELLS - A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer. | 10-27-2011 |
20110287612 | Nonvolatile Memory Device, Method of Manufacturing the Nonvolatile Memory Device, and Memory Module and System Including the Nonvolatile Memory Device - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer. | 11-24-2011 |
20110316165 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines. | 12-29-2011 |
20120037975 | SEMICONDUCTOR DEVICES - A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein. | 02-16-2012 |
20120045890 | Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines - A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed. | 02-23-2012 |
20120058629 | METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves. | 03-08-2012 |
20120086072 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE - A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent. | 04-12-2012 |
20120122297 | METHOD OF FABRICATING A NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps. | 05-17-2012 |
20120146118 | NON-VOLATILE MEMORY DEVICE WITH HIGH SPEED OPERATION AND LOWER POWER CONSUMPTION - A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be. | 06-14-2012 |
20120202335 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 08-09-2012 |
20120210823 | METHOD OF HARDENING AN INTERFACE OF CARBON MATERIAL USING NANO SILICON CARBIDE COATING - Disclosed is a method for hardening an interface of a carbon material by using nano silicon carbide coating. A carbon material-aluminum composite prepared by the disclosed method is light in weight, and has a high dynamic strength, and thus can be applied to currently used cars and aluminum wheels. Furthermore, the composite can be utilized as a material for aircrafts, spacecraft, ships, etc. requiring a high strength. | 08-23-2012 |
20120218816 | Non-Volatile Memory Devices - A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines. | 08-30-2012 |
20120326225 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap. | 12-27-2012 |
20130115733 | ETCHANT COMPOSITION AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR USING THE SAME - Provided is an etchant composition. The etchant composition according to an exemplary embodiment of the present invention includes ammonium persulfate ((NH | 05-09-2013 |
20130252391 | NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND MEMORY MODULE AND SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer. | 09-26-2013 |
20140231953 | NAND FLASH MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps. | 08-21-2014 |
20140248755 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 09-04-2014 |
20150008499 | VERTICAL SEMICONDUCTOR DEVICE - A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction. | 01-08-2015 |
20150060977 | SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL STRUCTURES - Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width. | 03-05-2015 |
20150060993 | NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND MEMORY MODULE AND SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer. | 03-05-2015 |
20150097222 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A channel layer is formed on a substrate. The channel layer is extended in a first direction substantially perpendicular to an upper surface of the substrate. A ground selection line is formed on a first region of the channel layer. A plurality of word lines is formed on a second region of the channel layer. A plurality of string selection lines is formed on a third region of the channel layer. The second region of the channel layer includes a first conductivity type dopant. The first, second and third regions of the channel layer are disposed along the first direction. | 04-09-2015 |
20150129878 | SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region. | 05-14-2015 |
20150132906 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 05-14-2015 |
20150132915 | Non-Volatile Memory Devices and Manufacturing Methods Thereof - There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer | 05-14-2015 |
20150194332 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap. | 07-09-2015 |
20150325588 | SEMICONDUCTOR DEVICES - A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other. | 11-12-2015 |
Patent application number | Description | Published |
20100129373 | VEGF-SPECIFIC HUMAN ANTIBODY - The present invention relates to a vascular endothelial growth factor (VEGF)-specific human antibody, and more particularly to a human antibody including a complementarity determining region (CDR) and a framework region (FR) derived from a human antibody specifically bound to VEGF. The VEGF-specific human antibody of the present invention may be used in diagnosis of diseases caused by the VEGF-overexpression, classification of the diseases, visualization, treatment, and prognostic evaluation. | 05-27-2010 |
20110065176 | HUMAN MONOCLONAL ANTIBODY NEUTRALIZING VASCULAR ENDOTHELIAL GROWTH FACTOR RECEPTOR AND USE THEREOF - The present invention relates to human monoclonal antibodies neutralizing vascular endothelial growth factor receptor and the use thereof. More specifically, relates to human ScFv molecules neutralizing vascular endothelial growth factor receptor, and a composition for inhibiting angiogenesis and a composition for treating cancer, which contain the human ScFv molecules. The disclosed monoclonal antibody neutralizing vascular endothelial growth factor receptor shows excellent neutralizing ability in living cells, compared to that of a commercially available antibody against vascular endothelial growth factor receptor, and shows the ability to neutralize vascular endothelial growth factor receptor not only in humans, but also in mice and rats. Thus, the monoclonal antibody will be useful in anticancer studies and will be highly effective in cancer treatment. | 03-17-2011 |
20110189087 | TMPRSS4-Specific Human Antibody - The present invention relates to a transmembrane protease, serine (TMPRSS4)-specific human antibody, and more particularly to a human antibody including a complementarity determining region (CDR) and a framework region (FR) derived from a human antibody specifically bound to TMPRSS4. The TMPRSS4-specific human antibody expressed in the various kinds of cancer cells of the present invention may be used in diagnosis of the cancer, classification of the disease, visualization, treatment, and prognostic evaluation. | 08-04-2011 |
20110195027 | CD9-SPECIFIC HUMAN ANTIBODIES - The present invention relates to a CD9-specific human antibody, more precisely a CD9-specific human antibody composed of human derived CD9-specific complementarity determining region (CDR) and framework region (FR). The human antibody of the present invention recognizes CD9 extracellular loop 2 domain (CD9-ECL2) as an epitope and thereby strongly binding thereto. The human antibody of the present invention also has CD9 antigen neutralizing effect and at the same time inhibiting effect on tumor cell lines. Therefore, it can be effectively used for the prevention and treatment of cancer overexpressing CD9. | 08-11-2011 |
20120039911 | CD93 OR USE OF SOLUBLE FRAGMENT THEREOF - The present invention relates to an anti-inflammatory composition using the antibody specifically binding to CD93 or its soluble fragment, and a diagnostic method and a diagnostic kit for inflammatory disease using CD93 or its soluble fragment specific antibody or aptamer. | 02-16-2012 |
20120308574 | HUMAN MONOCLONAL ANTIBODY THAT SPECIFICALLY BINDS TO VCAM-1 AND A COMPOSITION FOR TREATING AN INFLAMMATORY DISEASE OR A CANCER COMPRISING THE SAME - The present invention relates to a human monoclonal antibody that specifically binds to VCAM-1, and a therapeutic composition for the treatment of inflammatory disease or cancer comprising the same. The human monoclonal antibody according to the present invention shows a strong affinity to VCAM-1 expressed on human or mouse endothelial cell, effectively inhibits leukocyte adhesion to activated endothelial cells expressing VCAM-1, and shows a low immunogenicity, thereby being used for the treatment of cancer or inflammatory disease such as asthma, rhinitis, arthritis, multiple sclerosis, bowel disease, arteriosclerosis, myocardial infarction and transplant rejection. | 12-06-2012 |
20130017226 | TNF-A and TWEAK Dual Antagonist for the Prophylaxis and Treatment of Autoimmune DiseasesAANM Park; Young WooAACI DaejeonAACO KRAAGP Park; Young Woo Daejeon KRAANM Jo; Ki WonAACI Gyeonggi-doAACO KRAAGP Jo; Ki Won Gyeonggi-do KRAANM Yoo; Srok HoAACI DaejeonAACO KRAAGP Yoo; Srok Ho Daejeon KRAANM Yu; JungAACI DaejeonAACO KRAAGP Yu; Jung Daejeon KRAANM Kim; Dong JiAACI DaejeonAACO KRAAGP Kim; Dong Ji Daejeon KRAANM Yoon; Sun-HaAACI DaejeonAACO KRAAGP Yoon; Sun-Ha Daejeon KRAANM Song; Eun JungAACI DaejeonAACO KRAAGP Song; Eun Jung Daejeon KRAANM Lee; Eun KyungAACI Gyeonggi-doAACO KRAAGP Lee; Eun Kyung Gyeonggi-do KRAANM Oh; Jin MiAACI Gyeonggi-doAACO KRAAGP Oh; Jin Mi Gyeonggi-do KRAANM Cho; Kyu WonAACI SeoulAACO KRAAGP Cho; Kyu Won Seoul KRAANM Cho; Mi LaAACI SeoulAACO KRAAGP Cho; Mi La Seoul KRAANM Kim; Ho YounAACI SeoulAACO KRAAGP Kim; Ho Youn Seoul KRAANM Park; Mi KyungAACI Gyeonggi-doAACO KRAAGP Park; Mi Kyung Gyeonggi-do KRAANM Oh; Hye JwaAACI SeoulAACO KRAAGP Oh; Hye Jwa Seoul KRAANM Park; Jin SilAACI SeoulAACO KRAAGP Park; Jin Sil Seoul KRAANM Woo; Yun JuAACI SeoulAACO KRAAGP Woo; Yun Ju Seoul KRAANM Byun; Jae KyeongAACI Chungcheongbuk-doAACO KRAAGP Byun; Jae Kyeong Chungcheongbuk-do KRAANM Ryu; Jun GeolAACI Gangwon-doAACO KRAAGP Ryu; Jun Geol Gangwon-do KR - The present invention relates to TNFR2-TWEAKR fusion protein, more precisely to TNFR2-TWEAKR fusion protein acting as a double-antagonist to TNF-α and TWEAK, known as major causes of autoimmune arthritis which is one of autoimmune diseases. When the composition comprising TNFR2-TWEAKR fusion protein was treated to Th17 cells, the secretion of the inflammatory cytokine IL-17 was reduced but the secretion of the anti-inflammatory cytokine IL-10 generated in Treg cells was increased. Such effect of TNFR2-TWEAKR fusion protein was far greater than that of a single protein such as TNFR2-Fc or TWEAK-Fc. The TNFR2-TWEAKR fusion protein of the present invention has not only excellent treatment effect on arthritis in CIA mouse model not also excellent treatment effect on autoimmune rheumatoid arthritis by increasing the expression of Treg, the immune suppressive cells. Therefore, the TNFR2-TWEAKR fusion protein of the present invention can be effectively used as an active ingredient for the composition for the prevention and treatment of autoimmune disease. | 01-17-2013 |
20130022642 | Dual Antagonist for TNF-A and IL-21 for Preventing and Treating Autoimmune Diseases - The present invention relates to TNFR2-IL21R fusion protein acting as a double-antagonist to TNF-alpha (α) and IL-21. The composition containing the double antagonist to TNF-α and Il-21 (TNFR2-IL21R fusion protein), known as major causes of autoimmune rheumatoid arthritis, one of autoimmune diseases, can reduce the secretion of inflammatory cytokine, increase the secretion of anti-inflammatory cytokine, and suppress the differentiation of osteoclasts better than single proteins such as TNFR2-Fc and IL21R-Fc. The TNFR2-IL21R fusion protein of the present invention has not only excellent treatment effect on arthritis in CIA mouse model not also excellent treatment effect on autoimmune rheumatoid arthritis by increasing the expression of Treg, the immune suppressive cells. Therefore, the TNFR2-IL21R fusion protein of the present invention can be effectively used as an active ingredient for the composition for the prevention and treatment of autoimmune disease. | 01-24-2013 |
20140066375 | PHARMACEUTICAL COMPOSITION CONTAINING AN ENDOCYTIC MOTIF AND PROTEIN TRANSDUCTION DOMAINS FOR PREVENTING OR TREATING CANCER - The present invention relates to a novel endocytic motif, and in particular, to a fusion polypeptide including the motif represented by an amino acid sequence of SEQ ID NO. 1 and a protein transduction domain, a pharmaceutical composition for preventing or treating cancer including the same, and a method for treating cancer including the step of administering the composition. The present invention shows the effects of suppressing metastasis, infiltration, angiogenesis, and growth of cancer by specifically inhibiting c-Met endocytosis and effectively inhibiting HGF/c-Met signaling pathway associated with metastasis and growth of various types of cancer cells. Therefore, the present invention can be applied to an anticancer agent for various types of cancer. | 03-06-2014 |
20140275488 | HUMAN MONOCLONAL ANTIBODY NEUTRALIZING VASCULAR ENDOTHELIAL GROWTH FACTOR RECEPTOR AND USE THEREOF - The present invention relates to human monoclonal antibodies neutralizing vascular endothelial growth factor receptor and the use thereof. More specifically, relates to human ScFv molecules neutralizing vascular endothelial growth factor receptor, and a composition for inhibiting angiogenesis and a composition for treating cancer, which contain the human ScFv molecules. The disclosed monoclonal antibody neutralizing vascular endothelial growth factor receptor shows excellent neutralizing ability in living cells, compared to that of a commercially available antibody against vascular endothelial growth factor receptor, and shows the ability to neutralize vascular endothelial growth factor receptor not only in humans, but also in mice and rats. Thus, the monoclonal antibody will be useful in anticancer studies and will be highly effective in cancer treatment. | 09-18-2014 |
20140288274 | HUMAN MONOCLONAL ANTIBODY NEUTRALIZING VASCULAR ENDOTHELIAL GROWTH FACTOR RECEPTOR AND USE THEREOF - The present invention relates to human monoclonal antibodies neutralizing vascular endothelial growth factor receptor and the use thereof. More specifically, relates to human ScFv molecules neutralizing vascular endothelial growth factor receptor, and a composition for inhibiting angiogenesis and a composition for treating cancer, which contain the human ScFv molecules. The disclosed monoclonal antibody neutralizing vascular endothelial growth factor receptor shows excellent neutralizing ability in living cells, compared to that of a commercially available antibody against vascular endothelial growth factor receptor, and shows the ability to neutralize vascular endothelial growth factor receptor not only in humans, but also in mice and rats. Thus, the monoclonal antibody will be useful in anticancer studies and will be highly effective in cancer treatment. | 09-25-2014 |
20150110815 | DRUG CONJUGATE COMPRISING DRUG LINKED TO HUMAN C-MET ANTIBODY, AND USE THEREFOR - The present invention relates to a drug conjugate comprising a cytotoxic drug conjugated to a c-Met specific human antibody. More specifically, the present invention relates to: a drug conjugate comprising a cytotoxic drug conjugated to a c-Met specific human antibody; a pharmaceutical composition for cancer treatment comprising the drug conjugate; and a cancer treatment method comprising a step in which the drug conjugate or pharmaceutical composition is administered to an individual. | 04-23-2015 |