Patent application number | Description | Published |
20090168549 | Data output buffer circuit and semiconductor memory device includig the same - The example embodiments provide a data output buffer circuit which includes a pre-driver configured to adjust a slew rate of an input signal, a main driver configured to output signal supplied from the pre-driver, and a ZQ calibration circuit configured to control the pre-driver so as to decrease the slew rate when an operation voltage increases, and increase the slew rate when the operation voltage is decreased. | 07-02-2009 |
20110205832 | ON-DIE TERMINATION CIRCUIT, MEMORY DEVICE, MEMORY MODULE, AND METHOD OF OPERATING AND TRAINING AN ON-DIE TERMINATION - An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command. The memory device may further comprise a training circuit comprising: an asynchronous signal delay configured to delay the signal path of the ACS signal to the termination circuit; and a comparing unit configured to compare a phase difference between the ACS signal and a reference signal, the comparing unit comprising a phase detector and a replica delay, wherein the replica delay is configured to delay the signal path of the ACS signal to the phase detector, and the phase detector is configured to output the phase difference as training result. | 08-25-2011 |
20120250433 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 10-04-2012 |
20130099823 | OUTPUT DRIVER, DEVICES HAVING THE SAME, AND GROUND TERMINATION - An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal. | 04-25-2013 |
20130182513 | MEMORY SYSTEM CAPABLE OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE - Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller. | 07-18-2013 |
20130182524 | SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES - A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal. | 07-18-2013 |
20130201765 | POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal. | 08-08-2013 |
20130257534 | INPUT RECEIVER CIRCUIT HAVING SINGLE-TO-DIFFERENTIAL AMPLIFIER, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal. | 10-03-2013 |
20140286119 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 09-25-2014 |
20150016202 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 01-15-2015 |