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Young-Hee Kim

Young-Hee Kim, Yorktown Heights, NY US

Patent application numberDescriptionPublished
20090008719METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS - A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.01-08-2009
20090008720METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS - A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.01-08-2009
20090011552METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS - A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.01-08-2009
20090142891MASKLESS STRESS MEMORIZATION TECHNIQUE FOR CMOS DEVICES - In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device, wherein the NFET device includes an amorphous silicon containing region; depositing a tensile strain silicon nitride layer atop the NFET device and the PFET device, wherein the silicon nitride tensile strain layer induces a tensile strain in a channel of the NFET device region; annealing to crystallize the amorphous silicon containing region, wherein the tensile strain silicon nitride layer positioned atop the PFET device confines oxygen within a channel positioned within the silicon containing substrate underlying the PFET device, wherein the oxygen within the channel shifts a threshold voltage of the PFET device towards a valence band of silicon of the silicon containing substrate; and removing the tensile strain silicon nitride layer.06-04-2009
20090302399Using Metal/Metal Nitride Bilayers as Gate Electrodes in Self-Aligned Aggressively Scaled CMOS Devices - The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.12-10-2009
20100041221HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME - The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.02-18-2010
20110007761TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES - Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.01-13-2011
20130137202TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES - Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.05-30-2013

Patent applications by Young-Hee Kim, Yorktown Heights, NY US

Young-Hee Kim, Mohegan Lake, NY US

Patent application numberDescriptionPublished
20080308872CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS - An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.12-18-2008
20090206413CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE - A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.08-20-2009
20100038736SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE - A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.02-18-2010
20100148273CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS - An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.06-17-2010
20100244206METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS - A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.09-30-2010
20110143482SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE - A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.06-16-2011
20110308583PLASMA TREATMENT AT A P-I JUNCTION FOR INCREASING OPEN CIRCUIT VOLTAGE OF A PHOTOVOLTAIC DEVICE - Open circuit voltage of a photovoltaic device including a p-i-n junction including amorphous silicon-containing semiconductor materials is increased by a high power plasma treatment on an amorphous p-doped silicon-containing semiconductor layer before depositing an amorphous intrinsic silicon-containing semiconductor layer. The high power plasma treatment deposits a thin layer of nanocrystalline silicon-containing semiconductor material or converts a surface layer of the amorphous p-doped silicon containing layer into a thin nanocrystalline silicon-containing semiconductor layer. After deposition of an intrinsic amorphous silicon layer, the thin nanocrystalline silicon-containing semiconductor layer functions as an interfacial nanocrystalline silicon-containing semiconductor layer located at a p-i junction. The increase in the open circuit voltage of the photovoltaic device through the plasma treatment depends on the composition of the interfacial crystalline silicon-containing semiconductor layer, and particularly on the atomic concentration of carbon in the interfacial crystalline silicon-containing semiconductor layer.12-22-2011
20110308584SURFACE TREATMENT OF TRANSPARENT CONDUCTIVE MATERIAL FILMS FOR IMPROVEMENT OF PHOTOVOLTAIC DEVICES - A tunneling layer is provided between a transparent conductive material and a p-doped semiconductor layer of a photovoltaic device. The tunneling layer is comprised of stoichiometric oxides which are formed when an upper surface of the transparent conductive material is subjected to one of the surface modification techniques of this disclosure. The surface modification techniques oxidize the dangling metal bonds of the transparent conductive material. The tunneling layer acts as a protective layer for the transparent conductive material. Moreover, the tunneling layer improves the interface between the transparent conductive material and the p-doped semiconductor layer. The improved interface that exists between the transparent conductive material and the p-doped semiconductor layer results in enhanced properties of the resultant photovoltaic device containing the same. In some embodiments, a high quality single junction solar cell can be provided by this disclosure that has a very well defined interface.12-22-2011
20110308585DUAL TRANSPARENT CONDUCTIVE MATERIAL LAYER FOR IMPROVED PERFORMANCE OF PHOTOVOLTAIC DEVICES - A dual transparent conductive material layer is provided between a p-doped semiconductor layer and a substrate layer of a photovoltaic device. The dual transparent conductive material layer includes a first transparent conductive material and a second transparent conductive material wherein the second transparent conductive material is nano-structured. The nano-structured second transparent conductive material acts as a protective layer for the underlying first transparent conductive material. The nano-structured transparent conductive material provides a benefit of a higher Eg of the underlying first transparent conductive material surface and a very high resilience to hydrogen plasma from the nano-structures during the formation of the p-doped semiconductor layer.12-22-2011
20120125916TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES - Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.05-24-2012
20120322200NON-LITHOGRAPHIC METHOD OF PATTERNING CONTACTS FOR A PHOTOVOLTAIC DEVICE - A dielectric material layer is formed on a front surface of a photovoltaic device. A patterned PMMA-type-material-including layer is formed on the dielectric material layer, and the pattern is transferred into the top portion of the photovoltaic device to form trenches in which contact structures can be formed. In one embodiment, a blanket PMMA-type-material-including layer is deposited on the dielectric material layer, and is patterned by laser ablation that removes ablated portions of PMMA-type-material. The PMMA-type-material-including layer may also include a dye to enhance absorption of the laser beam. In another embodiment, a blanket PMMA-type-material-including layer may be deposited on the dielectric material layer and mechanically patterned to form channels therein. In yet another embodiment, a patterned PMMA-type-material-including layer is stamped on top of the dielectric material layer.12-20-2012
20130025663INVERTED PYRAMID TEXTURE FORMATION ON SINGLE-CRYSTALLINE SILICON - A method for texturing a single-crystalline silicon substrate is provided in which inverted pyramids are formed within the textured single-crystalline silicon substrate. The textured single-crystalline silicon substrates containing the inverted pyramids provided by the present disclosure have a low reflectance associated therewith and thus can be used as a component of a silicon solar cell. The method includes forming a plurality of openings that extend beneath an upper surface of a single-crystalline silicon substrate, and forming inverted pyramids in each of the openings by expanding each opening.01-31-2013
20130032865FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1002-07-2013
20130032883FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1002-07-2013
20130045562BURIED SELECTIVE EMITTER FORMATION FOR PHOTOVOLTAIC DEVICES UTILIZING METAL NANOPARTICLE CATALYZED ETCHING - A method of forming a photovoltaic device containing a buried emitter region and vertical metal contacts is provided. The method includes forming a plurality of metal nanoparticles on exposed portions of a single-crystalline silicon substrate that are not covered by patterned antireflective coatings (ARCs). A metal nanoparticle catalyzed etching process is then used to form trenches within the single-crystalline silicon substrate and thereafter the metal nanoparticles are removed from the trenches. An emitter region is then formed within exposed portions of the single-crystalline silicon substrate, and thereafter a metal contact is formed atop the emitter region.02-21-2013
20130140634METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION - A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.06-06-2013
20140000691INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING01-02-2014
20140000693INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING01-02-2014
20140015051METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION - A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.01-16-2014
20140103286INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE - The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.04-17-2014
20140148003REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK - Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.05-29-2014
20150064897PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES - Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.03-05-2015

Patent applications by Young-Hee Kim, Mohegan Lake, NY US

Young-Hee Kim, Gwacheon-Si KR

Patent application numberDescriptionPublished
20090104467SURFACE PROTECTIVE FILM, METHOD FOR FABRICATING THE SAME, POUCH THEREOF AND METHOD FOR FABRICATING THE SAME - Disclosed is a surface protective film, a method for fabricating the same, and pouch, and a method for fabricating the same. The surface protective film includes a stack of films including a middle layer, and a first skin layer and a second skin layer on opposite sides of the middle layer, wherein at least one of the first skin layer and the second skin layer is formed of a resin having a hardness lower than a hardness of a surface to be protected by the surface protective film, and the middle layer is formed of a resin including high density polyethylene, thereby permitting protection of a display surface without formation of scratch at a very low cost compared to the related art without aging and with slip.04-23-2009
20100155278Protective film-integrated pouch - Disclosed is a protective film-integrated pouch wherein a protective film to protect a display panel and a bag to cover and package the display panel are integrally formed. The protective film-integrated pouch includes a rectangular body, including upper and lower layers, the body having three sealed edges and one opened edge to define an opening, allowing insertion of a display panel into the pouch, wherein each of the upper layer and the lower layer includes a base layer made of a metallic material, an outer surface layer disposed on the base layer, and an inner surface layer disposed on the outer surface layer, wherein the inner surface layer contacts the display panel and is made of a mixed polyethylene resin.06-24-2010
20100247832Label and Method for Preparing the Same - Disclosed is a label comprising a substrate film, or a substrate film and an intermediate film, wherein either or both of the substrate film and the intermediate film have through-holes, and a method for preparing the same. The method for preparing the label causes no generation of defects, and shows an excellent production rate and work efficiency. The label has no possibility of forgery, and shows clear marking characteristics. In addition, the label has a simple structure and excellent printability and cost efficiency, causes no degradation of the quality with time, shows high chemical resistance and heat resistance, is free from various contaminants during use, and is provided with low initial adhesion but high permanent adhesion.09-30-2010
20110111142LABEL AND METHOD OF MANUFACTURING THE SAME - Disclosed are a label and a method of manufacturing the same, the label comprising: a first base film; a first ink layer formed on the exterior top part of the first base film, and comprising a metal or metal oxide that changes from its original color to another color by being oxidized by a laser; and a resin coating layer coated on the first ink layer to protect the first ink layer, wherein the laser passing through a part or the whole of the resin coating layer is transmitted to the first ink layer. According to the present invention, there is no oxidation residue; thus, the efficiency of marking is excellent and any possibility of change in quality due to aging can be eliminated. In addition, the color rendering is excellent, and the scratch resistance, chemical resistance and heat resistance are superior.05-12-2011

Patent applications by Young-Hee Kim, Gwacheon-Si KR

Young-Hee Kim, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20110212361CELL PACKAGING MATERIAL AND METHOD FOR PRODUCING THE SAME - Provided is a cell packaging material having a layered structure of one or more layers, wherein at least one layer includes a flame retardant, a coating layer imparted with flame resistance, or both. In the cell packaging material, a cell itself does not include any flame resistant film or flame retardant. Therefore, it is possible to provide a cell with flame resistance while not increasing the cell volume or not affecting the cell operation.09-01-2011

Young-Hee Kim, Austin, TX US

Patent application numberDescriptionPublished
20120315752METHOD OF FABRICATING NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.12-13-2012

Young-Hee Kim, Gangwon-Do KR

Patent application numberDescriptionPublished
20140017333METHOD FOR FERMENTING ANTLERS, VENISON, OR DEER BONES USING MUSHROOMS, AND RESULTANT FERMENTED PRODUCTS - The present invention relates to a method of fermenting velvet antler (or venison or deer bone) together with a mushroom concentration in order to increase the efficacy thereof, and a fermentation product obtained thereby. In accordance with the present invention, velvet antler is fermented in a state in which it was not concentrated or ground, and the shape thereof is maintained after fermentation. Thus, the loss of velvet antler is insignificant, and the fermented velvet antler has a high efficacy and can be used in various shapes in subsequent processes.01-16-2014

Young-Hee Kim, Chanwon-Si KR

Patent application numberDescriptionPublished
20150138892SINGLE POLY EEPROM DEVICE - The present invention proposes a single poly EEPROM cell including a first control gate capacitor, a first tunnel gate capacitor, a first sense transistor, and a first selection transistor. In a single poly EEPROM cell according to the present invention, a Fowler Nordheim (FN) tunneling method is used in order to increase the recognition distance of an RFID tag chip in mode. In a single poly EEPROM device including a single poly EEPROM cell, the single poly EEPROM cell includes a first control gate capacitor MC05-21-2015
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