Patent application number | Description | Published |
20080259669 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPTIMIZING SIGNAL TRANSMISSION POWER AND POWER INITIALIZING METHOD THEREOF - A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal. | 10-23-2008 |
20090016476 | Method for shifting a phase of a clock signal and memory chip using the same - A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error. | 01-15-2009 |
20090020863 | Stacked semiconductor devices and signal distribution methods thereof - A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique. | 01-22-2009 |
20090085599 | Semiconductor device having ESD protection circuit and method of testing the same - A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally. | 04-02-2009 |
20090115473 | LOOP FILTER, PHASE-LOCKED LOOP, AND METHOD OF OPERATING THE LOOP FILTER - A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current. | 05-07-2009 |
20090127668 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF - A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed. | 05-21-2009 |
20090140785 | Duty detector and duty cycle corrector including the same - A duty detector includes a clock converter, a hold pulse generator, a first logic operator, and an up/down counter. The clock converter receives a clock signal to generate an up clock signal and a down clock signal having phases opposite to each other. The hold pulse generator generates a hold pulse signal that is deactivated during a counting interval corresponding to first through (N−1)-th period intervals of the clock signal and is activated during a holding interval corresponding to an N-th period interval. The first logic operator outputs a counting clock signal by performing a first logic operation on the hold pulse signal and a sampling clock signal. The up/down counter determines a logic level of the up clock signal and a logic level of the down clock signal at an edge timing of the counting clock signal, increases or decreases a counting value in response to the determination result, and outputs duty information of the clock signal, based on a final counting value. | 06-04-2009 |
20090285032 | Self pre-charging and equalizing bit line sense amplifier - A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors. | 11-19-2009 |
20100037108 | HIGH-SPEED SEMICONDUCTOR MEMORY TEST DEVICE - A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference clock signal, a clock converting unit receiving the reference clock signal and converting the frequency of the reference clock signal to a second clock signal in response to the control signal, and a test data converting unit receiving the first test data, converting the first test data to second test data synchronously with the second clock signal and providing the second test data to a semiconductor memory device under test. | 02-11-2010 |
20100225364 | Stacked semiconductor devices and signal distribution methods thereof - A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique. | 09-09-2010 |
20100277995 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPTIMIZING SIGNAL TRANSMISSION POWER AND POWER INITIALIZING METHOD THEREOF - A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal. | 11-04-2010 |
20100309715 | STABLE CURRENT SUPPLY CIRCUIT IRRESPECTIVE OF PVT VARIATIONS AND SEMICONDUCTOR HAVING SAME - A current supply circuit comprises a reference voltage generator generating a reference voltage that varies with temperature, a current circuit generating a constant reference current irrespective of the temperature based on the reference voltage, and a current source generating a mirror current by mirroring a base current as a replica current of the reference current. | 12-09-2010 |
20110031601 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF - A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed. | 02-10-2011 |
20120039141 | VOLTAGE CONTROL METHOD AND MEMORY DEVICE USING THE SAME - A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage. | 02-16-2012 |
20120064827 | SEMICONDUCTOR DEVICE INCLUDING COUPLING CONDUCTIVE PATTERN - A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern. | 03-15-2012 |
20120120736 | Self Pre-Charging and Equalizing Bit Line Sense Amplifier - A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors. | 05-17-2012 |
20120161780 | SEMICONDUCTOR DEVICE, TEST METHOD, AND TEST APPARATUS - A semiconductor device includes; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and generating a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, such that the level of the test current is defined by the level of the bias current. | 06-28-2012 |
20120176830 | VARIABLE RESISTANCE MEMORY DEVICES USING READ MIRROR CURRENTS - A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node. | 07-12-2012 |
20130077374 | STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION - A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits. | 03-28-2013 |
20130208530 | RESISTIVE MEMORY DEVICE, OPERATING METHOD, AND MEMORY SYSTEM - A resistive memory device includes a plurality of first switches that connect word lines to a ground line in response a first switch control signal and a plurality of second switches that connect a plurality of global bit lines to a plurality of local bit lines corresponding to the plurality of global bit lines in response to a second switch control signal. | 08-15-2013 |
20130308377 | Sensing Circuits And Phase Change Memory Devices Including The Same - A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current. | 11-21-2013 |
20140177321 | NONVOLATILE MEMORY DEVICE AND RELATED OPERATING METHOD - A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells. | 06-26-2014 |