| Patent application number | Description | Published |
|---|
| 20080219401 | SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY APPARATUS CONTAINING THE SAME - Threshold voltage shifts of transistors which are constituents of a bidirectional shift register are reduced to prevent a malfunction in the shift register. A bidirectional unit shift register includes first and second pull-down circuits ( | 09-11-2008 |
| 20080303769 | IMAGE DISPLAY DEVICE AND DRIVE CIRCUIT - The present invention aims to provide an image display device capable of reducing power consumption, and a drive circuit used in the same. The present invention relates to an image display device including signal lines, scanning lines, lines, transistors, capacitances, and a drive circuit. The drive circuit of the image display device has configuring active elements of a same conductivity type and has the active elements simultaneously formed on a same substrate as said transistor; and includes switching circuits for generating a first switching signal and a second switching signal for switching a voltage level of a drive signal based on a predetermined signal, and outputting the signals, an output level holding circuit for holding the voltage levels of the first switching signal and the second switching signal for a predetermined period based on a repeating signal, and an output circuit for generating the drive signal based on the first switching signal and the second switching signal, and outputting the drive signal to the line. | 12-11-2008 |
| 20090122951 | SHIFT REGISTER CIRCUIT - A bidirectional shift register in which an operation margin is not lowered when a shift direction of a signal is switched is provided. A unit shift register SR | 05-14-2009 |
| 20090231015 | DRIVER CIRCUIT - An object is to provide a driver circuit as well as a level converting circuit, capable of reducing current consumption and accelerating an operation, and in the driver circuit that changes a voltage level of an output signal in correspondence with a change in voltage level of an input signal, when a transistor is turned on and a voltage level of an output signal changes, a positive feedback operation of raising a voltage of an output node of an input stage circuit that drives the transistor is performed, whereby a gate-source voltage of the transistor increases while an on-resistance thereof decreases, and a change in voltage level of the output node in the positive feedback operation is accelerated due to a bootstrap action in the input stage circuit. | 09-17-2009 |
| 20100111245 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region. | 05-06-2010 |
| 20100166136 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal. | 07-01-2010 |
| 20100201666 | ELECTRO-OPTICAL DEVICE, SHIFT REGISTER CIRCUIT, AND SEMICONDUCTOR DEVICE - An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver. | 08-12-2010 |
| 20110025399 | AMPLITUDE CONVERSION CIRCUIT - In an amplitude conversion circuit that converts an input signal having a small amplitude into an output signal having a large amplitude, the input signal is supplied to a gate of a transistor that discharges an output terminal through a capacitance element. A charging/discharging circuit causes a gate voltage of the transistor to be substantially equal to a threshold voltage during an inactive period of the input signal. | 02-03-2011 |
| 20110122988 | Semiconductor device and shift register circuit - A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level. | 05-26-2011 |
| 20110142191 | SHIFT REGISTER CIRCUIT - A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit. | 06-16-2011 |
| 20110148954 | IMAGE DISPLAY APPARATUS - For an image display apparatus, cost reduction is enabled to prevent display errors while ensuring operational margin to prevent display errors even when the delay time of gate line driving signals is large. A source driver of a liquid-crystal display apparatus includes a data latch circuit for supplying display data to a decode circuit. A gate line inactivation transition detecting circuit detects inactivation of each of a plurality of gate lines and activates a detect signal for a certain period with that timing. The data latch circuit updates the held display data in response to activation of the detect signal. | 06-23-2011 |
| 20110182399 | SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY COMPRISING THE SAME - In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level. | 07-28-2011 |
| 20110222645 | SCANNING LINE DRIVING CIRCUIT - Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period. | 09-15-2011 |
| 20110228893 | SHIFT REGISTER CIRCUIT - A shift register circuit includes a first transistor which supplies a clock signal to an output terminal, and an inverter which drives a second transistor for discharging a gate of the first transistor. An input node of the inverter is separated from the gate of the first transistor, and the gates of the first and second transistors are charged and discharged by separate circuits, respectively. | 09-22-2011 |
| 20110274236 | SHIFT REGISTER CIRCUIT - An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period). | 11-10-2011 |
| 20110291712 | SCANNING-LINE DRIVE CIRCUIT - A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals. | 12-01-2011 |
| 20120027160 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region. | 02-02-2012 |
| 20120183117 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal. | 07-19-2012 |
| 20120207266 | SHIFT REGISTER CIRCUIT - A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit. | 08-16-2012 |
| 20130108006 | SHIFT REGISTER CIRCUIT | 05-02-2013 |
| 20130222220 | ELECTRO-OPTICAL DEVICE, SHIFT REGISTER CIRCUIT, AND SEMICONDUCTOR DEVICE - An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver. | 08-29-2013 |
| 20130272487 | SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY COMPRISING THE SAME - In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level. | 10-17-2013 |
| 20130301793 | SHIFT REGISTER CIRCUIT - An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period). | 11-14-2013 |
| 20140079174 | SHIFT REGISTER CIRCUIT - An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period). | 03-20-2014 |
| 20140117358 | ELECTRO-OPTICAL DEVICE, SHIFT REGISTER CIRCUIT, AND SEMICONDUCTOR DEVICE - An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver. | 05-01-2014 |
