Patent application number | Description | Published |
20080197494 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same - A semiconductor device has an interconnect and a via material. The via material is provided under the interconnect and is in contact with an end portion of the interconnect. The interconnect and the via are made of copper as one piece. The via material has a top surface coupled to a bottom surface of the interconnect. The top surface has a first portion parallel with a longitudinal direction of the interconnect and a second portion parallel with a direction perpendicular to the longitudinal direction, and the first portion is larger than the second portion. | 08-21-2008 |
20080211099 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 09-04-2008 |
20080252306 | Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device - A displacement detection pattern, usable for detection of a relative displacement between a wiring and a via plug, includes a wiring provided between via plugs and a conductor. The conductor is provided in the same layer level as a level at which the wiring is provided and is provided at a predetermined distance from the wiring. | 10-16-2008 |
20080285006 | METHOD OF MANFACTURING SEMICONDUCTOR DEVICE - To attain a method of manufacturing a semiconductor device using an exposure system capable of obtaining preferable resolution while an adverse effect caused by a reduction in depth-of-focus margin is prevented, there is provided a method of manufacturing a semiconductor device comprising exposing a first portion of a wafer with a first lens aperture, and exposing a second portion of the wafer with a second lens aperture. | 11-20-2008 |
20090085131 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes: a semiconductor substrate; a diffusion layer provided in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate; a gate electrode provided on the gate insulation film; and a Ni silicide layer selectively provided on the diffusion layer, and a metal cap film having Co as a main component is selectively provided on the Ni silicide layer. | 04-02-2009 |
20090159978 | SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING SAME - A semiconductor device | 06-25-2009 |
20090302451 | Semiconductor device having function circuits selectively connected to bonding wire - A semiconductor device includes a semiconductor chip, a wiring substrate, and wires. The semiconductor chip includes a first circuit, a second circuit having a function differing from that of the first circuit, a plurality of first pads disposed in a row along one side of the semiconductor chip and connected to the first circuit, and a plurality of second pads disposed between both of the first and second circuits and the first pads, and connected to the second circuit. The wiring substrate includes a plurality of terminals and the plurality of wires is connected between a plurality of terminals provided outside of the semiconductor chip, and ones of the first pads and the second pads. The wires are free from the other of the first pads and the second pads, and the plurality of the wires being not intersected to each other. | 12-10-2009 |
20090321842 | Method for manufacturing semiconductor device including metal gate electrode and semiconductor device - A first metal film mainly including Ta is formed on a gate insulating film in a region excluding an n MOS transistor formation region and then a polysilicon film is formed to cover the gate insulating film and the first metal film. A first dummy electrode is formed by selectively removing the gate insulating film and the polysilicon film by etching, and a second dummy gate is formed by selectively removing the gate insulating film, the first metal film and the polysilicon film. An insulating layer is formed to embed the dummy gate electrodes and to expose an upper surface of the dummy gate electrodes. The polysilicon film of the dummy gate electrodes is removed to form recesses in the insulating layer, then a second metal film is formed within the recesses and on the insulating layer, and the second metal film is selectively polished. | 12-31-2009 |
20100006932 | Semiconductor device and method of manufacturing the same - A semiconductor device, including: a first transistor formed on a substrate and including an Hf contained film as its gate insulating film; and a second transistor formed on said substrate and having the same conductive type as that of said first transistor, said second transistor including a silicon oxide film and not including an Hf contained film as its gate insulating film is provided. | 01-14-2010 |
20110241142 | Semiconductor device and manufacturing method of the semiconductor device - An MTJ element is formed in a wiring layer located in a lower tier and yet application of heat to the MTJ element is suppressed. A first insulating layer is formed over a substrate. Subsequently, the MTJ element is formed over the first insulating layer. After that a first wiring is formed over the MTJ element. Thereafter, a second insulating layer is formed over the first wiring. Then a second wiring is formed in the superficial layer of the second insulating layer. The second wiring is heat treated by photoirradiation. A shield conductor is formed at the step of forming the second wiring. | 10-06-2011 |
20110263113 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device | 10-27-2011 |
20120012843 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DESIGNING THE SAME - Unless layers over a TEG pattern are removed, a test using the TEG pattern is conducted. Multiple wiring layers are formed over a first TEG pattern. A wiring and multiple dummy patterns are formed in each of the wiring layers. An electrode pad is formed in an uppermost wiring layer. In a planar view, the first TEG pattern eliminates overlap with all of the wirings and the dummy patterns. | 01-19-2012 |
20140057432 | SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a first interconnect over the semiconductor substrate; forming an interlayer dielectric film over the first interconnect; forming a hole in the interlayer dielectric film such that the hole reaches the first interconnect; forming a trench in the interlayer dielectric film; and embedded a conductive film in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench, wherein, in a planar view, the first interconnect extends in a first direction, wherein, in a planar view, the second interconnect extends in a second direction which is perpendicular to the first direction, and wherein a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction. | 02-27-2014 |
20140306345 | SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first interconnect formed over the semiconductor substrate. An interlayer dielectric film is formed over the first interconnect, and a hole is formed in the interlayer dielectric film such that the hole reaches the first interconnect. A trench is formed in the interlayer dielectric film, and a conductive film is embedded in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench. In a planar view, the first interconnect extends in a first direction, the second interconnect extends in a second direction which is perpendicular to the first direction, and a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction. | 10-16-2014 |