Patent application number | Description | Published |
20090058399 | CLAMP JAW ASSEMBLY - A method of manufacturing a clamp jaw assembly for a clamp meter is provided. The method includes providing a clamp jaw core and a shield having a channel. The method further includes positioning the clamp jaw core within the channel of the shield such that the shield surrounds a portion of the clamp jaw core. The method also includes enclosing the clamp jaw core and the shield within a clamp jaw housing. | 03-05-2009 |
20090086872 | Method for binary clock and data recovery for fast acquisition and small tracking error - A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value. | 04-02-2009 |
20090161452 | Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design - A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced. | 06-25-2009 |
20090167443 | Digitally compensated highly stable holdover clock generation techniques using adaptive filtering - A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider. | 07-02-2009 |
20100007397 | Delay line circuit for generating a fixed delay - A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit. | 01-14-2010 |
20100007398 | Linear monotonic delay chain circuit - A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit. | 01-14-2010 |
20100008460 | Synchronous de-skew with programmable latency for multi-lane high speed serial interface - A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane. | 01-14-2010 |
20100261168 | Screening for Environmental DNAs Encoding Enzymes for Synthesizing Terpenoid-Based Therapeutic Compounds Using Genetically Modified E. Coli Strains - A screening method for identifying microbial genes involved in biosynthesis of therapeutic terpenoid-based compounds using genetically modified | 10-14-2010 |
20110098977 | HIGH SPEED CHIP SCREENING METHOD USING DELAY LOCKED LOOP - A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed. | 04-28-2011 |
20110101960 | CLAMP JAW ASSEMBLY - A clamp jaw assembly for a clamp meter is provided. The clamp jaw assembly comprises a housing containing a clamp jaw core disposed within a shield. The housing, shield, and core of the clamp jaw assembly are configured to provide an extended creepage and clearance path from an exterior of the housing to a surface of the core. | 05-05-2011 |
20110253192 | Solar Photovoltaic Assembly - The present invention relates to a solar photovoltaic assembly. The solar photovoltaic assembly, according to the invention, includes a solar panel, an input junction box, and an output junction box. The input junction box includes a first diode, a first electric connection body connected to the first diode, and first foils respectively spliced with the first electric connection body. The input junction box is positioned on a side of the second solar panel. The output junction box includes a second diode, a second electric connection body connected to the second diode, and second foils respectively spliced with the second electric connection body. The output second junction box positioned on another side of the solar panel. The input junction box mechanically and electrically connects to a second output junction box on a connecting solar panel using a cable. | 10-20-2011 |
20120023842 | Photovoltaic Panel Wall - The invention is a photovoltaic panel wall mounted on a building frame and has at least two photovoltaic assembly units. Each of the at least two photovoltaic assembly units includes an electrical connector having a male terminal and a female terminal that are configured to be detachably engaged. An opening is formed in the building frame, and one of the male and female terminals of the electrical connector is fixed in the opening. | 02-02-2012 |
20130002502 | MULTI-SYSTEM MULTI-BAND RFID ANTENNA - The present invention provides a multi-system multi-band RFID antenna, which comprises an on-chip antenna and at least one external antenna, wherein the on-chip antenna is arranged on RFID chip; the external antennas are arranged outside the RFID chip; and the RFID chip is provided with connection pads on the outer surface, wherein both the on-chip antenna and the external antennas are connected with the RFID chip through the connection pads. According to the multi-system multi-band RFID antenna of the present invention, the RFID chip can provide appropriate antennas for applications in different systems with different frequency bands, and can satisfactorily meet the need for RFID multi-system integration applications in the future. | 01-03-2013 |
20130050956 | Photovoltaic Junction Module - A photovoltaic junction module is provided, which includes a housing, an overmolded assembly, and a cable. The overmolded assembly includes an electrical assembly and a plastic body for enclosing the electrical assembly therein. The overmolded assembly is detachably mounted to the housing. The cable extends into the housing and detachably and electrically connects to the electrical assembly. | 02-28-2013 |
20130072039 | Solar Cell Connection Module - A solar cell connection module that includes a solar cell, a first junction box, and a second junction box. The solar cell panel includes a negative electrode and a positive electrode. The first junction box includes a first conductor, a second conductor, a first cable electrically connected to the second conductor, and a diode electrically connected between the first and second conductors. The first conductor is electrically connected to the negative electrode and the second conductor is electrically connected to the positive electrode so that the diode is electrically connected in parallel with the solar cell panel. The second junction box includes a conductor piece electrically connecting to the negative electrode and a second cable electrically connected to the conductor piece. | 03-21-2013 |
20130157675 | BASE STATION DEVICE, METHOD THEREOF, AND COMMUNICATION SYSTEM THEREOF - A base station device, a method thereof and a communication system thereof are disclosed. The base station comprises: a covariance matrix obtaining unit that forms a covariance matrix of an interference vector and a noise vector from received signals from multiple user equipments; a ratio calculation and comparison unit that calculates a relative ratio between the interference and the noise in the received signals based on the covariance matrix and compares the ratio with a predetermined threshold; an adjusting unit that reduces values of non-diagonal elements in the covariance matrix when the ratio is less than the predetermined threshold; an equalizer unit that performs equalization based on the covariance matrix by utilizing an Interference Rejection Combining algorithm when the ratio is greater than or equal to the predetermined threshold, and equalizes the received signals based on the adjusted covariance matrix by utilizing a Minimum Mean Square Error algorithm when the ratio is less than the predetermined threshold. By using the uniform receiver architecture, the advantages of the two algorithms are achieved in a simple structure, and further, its performance is superior to a MMSE receiver and an IRC receiver. | 06-20-2013 |
20130172414 | PHARMACEUTICAL COMPOSITION COMPRISING LEVOCARNITINE AND DOBESILATE - A pharmaceutical composition comprising levocarnitine and dobesilate is provided. Also provided are a method for regulating the level of serum creatinine and/or blood urea nitrogen and a method for treating and/or preventing the diseases influencing renal function, for example, including but not limiting to various primary, secondary nephritis, renal lesions, renal insufficiency, nephritic syndrome, even renal failure, uremia, as well as the complications induced by the diseases and/or disorders influencing renal function for example, such as cardiovascular diseases, diabetes and the like. | 07-04-2013 |
20130173994 | Variable Barrel Shifter - In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter. | 07-04-2013 |
20130314264 | DATA PROCESSING METHOD, AND RELEVANT DEVICES - A data processing method, a data processing system, and relevant devices are provided, which are used to reduce system power consumption. The method in embodiments of the present invention includes: performing sampling on an analog signal to obtain an analog sample value; performing analog-to-digital conversion on the analog sample value to obtain a digital signal; dividing bits forming the digital signal into at least two bit groups; and turning off output of bits in at least one bit group if a preset turnoff condition is satisfied. A data processing system and relevant devices are further provided. | 11-28-2013 |
20140112427 | COMPLETELY PASSIVE COOLING SYSTEM FOR REACTOR CORE AFTER ACCIDENT OF LARGE-SCALE PRESSURIZED WATER REACTOR NUCLEAR POWER PLANT - A passive cooling system for a reactor core of a large-scale pressurized water reactor nuclear power plant includes a shield building having an outer wall and a through air inlet arranged on an upper part of the outer wall, a water tank arranged at an upper part of the shield building, a cooling water distribution plate arranged above a top of a containment within the shield building, a spray pipe arranged at an inside of the top of the shield building and having a water inlet end and a water outlet end, wherein the water inlet end is connected to a bottom of the water tank and the water outlet end is extended to be above the cooling water distribution plate, and an air deflector arranged between the shield building and the containment and having an upper end connected to an inside of the top of the shield building. | 04-24-2014 |
20140234600 | COMPOSITE LAMINATE HAVING IMPROVED IMPACT STRENGTH AND THE USE THEREOF - A composite laminate having improved impact strength, which comprises: a multilayer carbon fiber fabric, wherein said carbon fiber fabric may be a bidirectional weave or a unidirectional weave; a multilayer nonwoven mat, wherein said nonwoven mat is made of para-aramid; and cured epoxy resin, wherein said cured epoxy resin is made of the epoxy resin system designed for impregnation that immersed in the carbon fiber fabric layer and at least one layer of the nonwoven mat is sandwiched between two layers of carbon fiber fabric layer and both outer surface layers of the composite laminate are carbon fiber fabric layer. | 08-21-2014 |
20150055259 | Whole-Chip Esd Protection Circuit and Esd Protection Method - A whole-chip Electrostatic Discharge (ESD) protection circuit and protection method are provided. The whole-chip ESD protection circuit comprises: input/output (I/O) units located between a power line and a grounding wire; a power clamp circuit located between the power line and the grounding wire and connected to the I/O units, any power clamp circuit being shared by multiple I/O units; and an ESD trigger circuit located between the power line and the grounding wire. The ESD trigger circuit generates an ESD trigger signal when an ESD events occurs and transmits the ESD trigger signal to the power clamp circuit and each I/O unit so that the power clamp circuit and each I/O unit form a current discharge path from the power line to the grounding wire respectively. Compared with the prior art, the present invention fully utilizes an existing driving transistor in the I/O unit to realize efficient whole-chip ESD protection and avoids adding too many power clamp circuits in the whole chip with regard to ESD, thereby reducing the overall size of the chip and lowering the cost. | 02-26-2015 |
20150060018 | HEAT PIPE BASED PASSIVE RESIDUAL HEAT REMOVAL SYSTEM FOR SPENT FUEL POOL - A heat pipe based passive residual heat removal system for a spent fuel pool has a plurality of partitions ( | 03-05-2015 |