Patent application number | Description | Published |
20090121292 | Fabrication of local damascene finFETs using contact type nitride damascene mask - Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices. | 05-14-2009 |
20090214277 | DEVELOPER STORAGE DEVICE AND IMAGE FORMING APPARATUS HAVING THE SAME - A developer storage device and an image forming apparatus having the same include a developer storage part including a first storage part and a second storage part having widths different from each other, and a first developer conveying member to convey a developer stored in the first storage part to the second storage part in a diagonal direction. The first developer conveying member includes conveying elements extended slantingly with respect to a width direction of the developer storage part. An angle between the conveying elements and the width direction of the developer storage part is determined depending on relative positions of the first storage part and the second storage part. Accordingly, the developer storage device can effectively convey a developer by designing the developer conveying member adequately for an overall shape or structure of the developer storage device. | 08-27-2009 |
20090317967 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. | 12-24-2009 |
20100248437 | Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures - A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease. | 09-30-2010 |
20130248984 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. | 09-26-2013 |
20140103482 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. | 04-17-2014 |
Patent application number | Description | Published |
20090114967 | TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME - According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved. | 05-07-2009 |
20100102384 | METAL OXIDE SEMICONDUCTOR (MOS) TRANSISTORS HAVING A RECESSED GATE ELECTRODE - A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region. | 04-29-2010 |
20110159569 | ANTI-NUCLEIC ACID ANTIBODY INDUCING CELL DEATH OF CANCER CELLS AND COMPOSITION FOR PREVENTING OR TREATING CANCERS COMPRISING THE SAME - There are provided an anti-nucleic acid antibody inducing cell death of cancer cells by invading normal cells; and a composition for preventing or treating cancers comprising the anti-nucleic acid antibody, which shows anticancer effect of an anti-nucleic acid antibody that shows cytotoxicity by damaging nucleic acid strands, that is, genetic information of a cancer cell when the anti-nucleic acid antibody, which has binding activity and degrading activity to the nucleic acid strands in cells at the same time, is overexpressed in the cancer cell, or flows in the cancer cell. Therefore, the composition for treating cancers may be useful to induce the selective cell death in cancer cells than in normal cells since the anti-nucleic acid antibody very easily permeates into the cancer cells due to the excellent selectivity, compared to the normal cells. | 06-30-2011 |
20120007175 | Metal Oxide Semiconductor (MOS) Transistors Having a Recessed Gate Electrode - A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region. | 01-12-2012 |
20120021993 | PROTEIN SCAFFOLD LIBRARY BASED ON KRINGLE DOMAIN STRUCTURE AND USES THEREOF - There are provided a Kringle domain structure, comprising: inducing artificial mutations at amino acid residues except for conserved amino acid residues that are important to maintain the structural scaffold of a Kringle domain; and protein scaffold variants, based on the Kringle domain structure, which modulate the biological activities of a variety of target molecules derived from the protein scaffold library by specifically binding to the target molecules. Also, there is provided a method for constructing homo-/hetero-oligomers which allow multi-specificity binding to multiple targets by the tandem assembly monomeric Kringle domain variants using a linker. Additionally, there is provided a method for preparing multispecific monomers and multivalent monomers by grafting target-binding loops of a Kringle domain variant into non-binding loops of another Kringle domain variant with the same or different target binding specificity. Furthermore, a protein scaffold variant based on the Kringle domain structure that specifically binds to target molecules, DNA encoding the protein scaffold variant, or a method and composition for prevention, detection, diagnosis, treatment or relieving diseases or disorders, particularly cancers and other immune-related diseases, comprising: administering an effective amount of the related molecule to animals, preferably human. | 01-26-2012 |
20130256629 | GRAPHENE SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, ORGANIC LIGHT EMITTING DISPLAY, AND MEMORY INCLUDING GRAPHENE SEMICONDUCTOR DEVICE - Graphene semiconductor device, a method of manufacturing a graphene semiconductor device, an organic light emitting display and a memory, include forming a multilayered member including a sacrificial substrate, a sacrificial layer, and a semiconductor layer deposited in sequence, forming a transfer substrate on the semiconductor layer, forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sacrificial substrate from the semiconductor layer, forming a second laminate by forming a graphene layer on a base substrate, combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer, and removing the transfer substrate. | 10-03-2013 |
Patent application number | Description | Published |
20080231184 | Higher efficiency incandescent lighting using photon recycling - A metallic photonic crystal (MPC) structure used as a filter with incandescent lighting is presented that significantly improves efficiency, while retaining the desirable color rendering index of incandescent lighting. The resulting efficiency is higher than many existing lighting types. The MPC filter is implemented with only a single layer of square lattice or two layers of woodpile-like lattice has high reflection from the photonic band edge to infinitely long wavelength. The MPC filter can be used in a spherical, cylindrical or flat form depending on the illumination scheme. | 09-25-2008 |
20130161677 | INTEGRATED POLARIZED LIGHT EMITTING DIODE WITH A BUILT-IN ROTATOR - The invention is directed to an integrated polarized light emitting diode device that has a light emitting diode, a metal grating, an oxide layer, and a built-in photonic crystal rotator. Additional teachings include a method for making the integrated polarized light emitting diode, a method for improving the polarization selectivity and energy efficiency of a light emitting diode, and a method for rotating polarization of a light emitting diode. | 06-27-2013 |
20130221323 | EFFICIENT AND DIRECTED NANO-LIGHT EMITTING DIODE, AND METHOD FOR MAKING SAME - The invention relates to light-emitting devices, and related components, systems and methods. In one aspect, the present invention is related to light emitting diode (LED) light extraction efficiency. A non-limiting example, the application teaches a method for improving light emitting diode (LED) extraction efficiency, by providing a nano-rod light emitting diode; providing quantum wells; and reducing the size of said nano-rod LED laterally in the quantum-well plane (x and y), thereby improving LED extraction efficiency. | 08-29-2013 |
Patent application number | Description | Published |
20130098540 | GRAPHENE-TRANSFERRING MEMBER, GRAPHENE TRANSFERRER, METHOD OF TRANSFERRING GRAPHENE, AND METHODS OF FABRICATING GRAPHENE DEVICE BY USING THE SAME - Graphene transferring members, graphene transferrer, methods of transferring graphene, and methods of fabricating a graphene device, may include a metal thin-film layer pattern and a graphene layer sequentially stacked on an adhesive member. The metal thin-film layer and the graphene layer may have the same shape. After transferring the graphene layer onto a transfer-target substrate during the fabrication of a graphene device, the metal thin-film layer is patterned to form electrodes on respective ends of the graphene layer by removing a portion of the metal thin-film layer. | 04-25-2013 |
20130193411 | GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a graphene device may include forming a device portion including a graphene layer on the first substrate; attaching a second substrate on the device portion of the first substrate; and removing the first substrate. The removing of the first substrate may include etching a sacrificial layer between the first substrate and the graphene layer. After removing the first substrate, a third substrate may be attached on the device portion. After attaching the third substrate, the second substrate may be removed. | 08-01-2013 |
20130193412 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer. | 08-01-2013 |
20130200789 | ELECTROMAGNETIC WAVE OSCILLATOR HAVING MULTI-TUNNEL AND ELECTROMAGNETIC WAVE GENERATING APPARATUS INCLUDING THE ELECTROMAGNETIC WAVE OSCILLATOR - Electromagnetic wave oscillators each having a multi-tunnel and electromagnetic wave generating apparatuses including the electromagnetic wave oscillators are provided. The electromagnetic wave oscillator includes: a first waveguide which has a folded structure such that a path traveled by an electromagnetic wave through the first waveguide crosses an axial direction a plurality of times; an electron beam tunnel through which an electron beam passes, wherein the electron beam tunnel extends along the axial direction and crosses the first waveguide a plurality of times; and at least one auxiliary tunnel which extends parallel to the electron beam tunnel and which crosses the first waveguide a plurality of times. | 08-08-2013 |
20140021446 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene. | 01-23-2014 |
20140030857 | GRAPHENE DEVICE MANUFACTURING APPARATUS AND GRAPHENE DEVICE MANUFACTURING METHOD USING THE APPARATUS - A graphene device manufacturing apparatus includes an electrode, a graphene structure including a metal catalyst layer formed on a substrate, a protection layer, and a graphene layer between the protection layer and the metal catalyst layer, a power unit configured to apply a voltage between the electrode and the metal catalyst layer, and an electrolyte in which the graphene structure is at least partially submerged. | 01-30-2014 |
20140061590 | GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from each other, forming a graphene layer having a portion defined as an active area between the first and second metal pads on the insulating material layer, forming third and fourth metal pads on the graphene layer spaced apart from each other with the active area therebetween, the third and fourth metal pads extending above the first metal pad and the second metal pad, respectively, forming a first protection layer to cover all the first and second metal pads, the graphene layer, and the third and fourth metal pads, and etching an entire surface of the first protection layer until only a residual layer made of a material for forming the first protection layer remains on the active area. | 03-06-2014 |
20140125310 | NANOGAP DEVICE AND METHOD OF PROCESSING SIGNAL FROM THE NANOGAP DEVICE - A nanogap device includes a first insulation layer having a nanopore formed therein, a first nanogap electrode which may be formed on the first insulation layer and may be divided into two parts with a nanogap interposed between the two parts, the nanogap facing the nanopore, a second insulation layer formed on the first nanogap electrode, a first graphene layer formed on the second insulation layer, a first semiconductor layer formed on the first graphene layer, a first drain electrode formed on the first semiconductor layer, and a first source electrode formed on the first graphene layer such as to be apart from the first semiconductor layer. | 05-08-2014 |
20140125322 | NANOGAP DEVICE AND METHOD OF PROCESSING SIGNAL FROM THE NANOGAP DEVICE - A nanogap device which may include a first insulation layer having a nanopore formed therein, a first channel layer which may be on the first insulation layer, a first source electrode and a first drain electrode which may be respectively in contact with both ends of the first channel layer, a second insulation layer which may cover the first channel layer, the first source electrode, and the first drain electrode, and a first nanogap electrode which may be on the second insulation layer and may be divided into two parts with a nanogap, which faces the nanopore, interposed between the two parts. | 05-08-2014 |
20140174640 | METHODS OF TRANSFERRING GRAPHENE AND MANUFACTURING DEVICE USING THE SAME - A method of transferring graphene includes forming a sacrificial layer and a graphene layer sequentially on a first substrate, bonding the graphene layer to a target layer, and removing the sacrificial layer using a laser and separating the first substrate from the graphene layer. | 06-26-2014 |
20140191198 | GRAPHENE ELECTRONIC DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene electronic device includes: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer. | 07-10-2014 |
20140335681 | GRAPHENE TRANSFERRING METHODS, DEVICE MANUFACTURING METHOD USING THE SAME, AND SUBSTRATE STRUCTURES INCLUDING GRAPHENE - Graphene transferring methods, a device manufacturing method using the same, and substrate structures including graphene, include forming a catalyst layer on a first substrate, forming a graphene layer on the catalyst layer, forming a protection metal layer on the graphene layer, attaching a supporter to the protection metal layer, separating the first substrate from the catalyst layer such that the protection metal layer, the graphene layer, and the catalyst layer remain on the supporter, removing the catalyst layer from the supporter, and transferring the protection metal layer and the graphene layer from the supporter to a second substrate. | 11-13-2014 |