Patent application number | Description | Published |
20140349073 | AEROSOL DEPOSITION COATING FOR SEMICONDUCTOR CHAMBER COMPONENTS - A method for coating a component for use in a semiconductor chamber for plasma etching includes providing the component and loading the component in a deposition chamber. A pressure in the deposition chamber is reduced to below atmospheric pressure. A coating is deposited on the component by spraying an aerosol comprising a suspension of a first type of metal oxide nanoparticle and a second type of metal oxide nanoparticle onto the component at approximately room temperature. | 11-27-2014 |
20140374843 | REPLACEMENT METAL GATE TRANSISTOR - A replacement metal gate transistor is described. Various examples provide a replacement metal gate transistor including a trench, a first sidewall and a second sidewall. A layer is disposed in the trench where the layer has a bottom section disposed on a bottom of the trench and sidewall sections disposed on the first and second sidewalls, wherein the sidewall sections of the layer are at least 50% thinner than the bottom section of the layer. | 12-25-2014 |
20140377885 | PROCESS FLOW FOR REPLACEMENT METAL GATE TRANSISTORS - A replacement metal gate transistor and methods of forming replacement metal gate transistors are described. Various examples provide methods of manufacturing a replacement metal gate transistor that includes depositing a dielectric layer into a trench, wherein the dielectric layer is deposited onto the bottom of the trench and the sidewalls of the trench, depositing a first metal layer into the trench, wherein the first metal layer is deposited onto the bottom of the trench and the sidewalls of the trench over the dielectric layer, depositing a second metal layer into the trench, wherein the second metal layer is deposited onto the bottom of the trench and the sidewalls of the trench over the first metal layer, removing at least a portion of the second metal layer from the sidewalls of the trench, and depositing a conducting layer into the trench. Other embodiments are disclosed and claimed. | 12-25-2014 |
20150021324 | ION ASSISTED DEPOSITION FOR RARE-EARTH OXIDE BASED COATINGS ON LIDS AND NOZZLES - A method of manufacturing an article comprises providing a lid or nozzle for an etch reactor. Ion assisted deposition (IAD) is then performed to deposit a protective layer on at least one surface of the lid or nozzle, wherein the protective layer is a plasma resistant rare earth oxide film having a thickness of less than 300 μm and an average surface roughness of 10 micro-inches or less. | 01-22-2015 |
20150024155 | ION ASSISTED DEPOSITION FOR RARE-EARTH OXIDE BASED THIN FILM COATINGS ON PROCESS RINGS - A method of manufacturing an article comprises providing a ring for an etch reactor. Ion assisted deposition (IAD) is then performed to deposit a protective layer on at least one surface of the ring, wherein the protective layer is a plasma resistant rare earth oxide film having a thickness of less than 300 μm and an average surface roughness of less than 6 micro-inches. | 01-22-2015 |
20150099347 | TRENCH FORMATION WITH CD LESS THAN 10 NM FOR REPLACEMENT FIN GROWTH - Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs. | 04-09-2015 |
20150118822 | METHODS FOR SILICON RECESS STRUCTURES IN A SUBSTRATE BY UTILIZING A DOPING LAYER - Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed. | 04-30-2015 |
20150140787 | TRIMMING SILICON FIN WIDTH THROUGH OXIDATION AND ETCH - Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs. | 05-21-2015 |