Patent application number | Description | Published |
20080284341 | PHOTO DETECTOR AND METHOD FOR FORMING THEREOF - A photo detector is disclosed. The photo detector has a substrate, a semiconductor layer disposed on the substrate, an insulating layer covered on the semiconductor layer, an interlayer dielectric layer covered on the insulating layer, and two electrodes formed on a portion of the interlayer dielectric layer. The semiconductor layer has a first doping region, a second doping region, and an intrinsic region located between the first doping region and the second doping region. The interlayer dielectric layer has at least three holes to expose a portion of the insulating layer, a portion of the first doping region, and the second doping region. The electrodes are connected to the first doping region and the second doping region through two of the holes. | 11-20-2008 |
20080296581 | Pixel structure and method for forming the same - A pixel structure including at least one thin-film transistor, at least one storage capacitor, a patterned first metal layer, an interlayer dielectric layer, a passivation layer, and a patterned pixel electrode is provided. The storage capacitor is electrically connected to the thin-film transistor. The patterned first metal layer is covered by the interlayer dielectric layer. The thin-film transistor and the interlayer dielectric layer are covered by the passivation layer, wherein an opening is formed in the passivation layer and a part of the interlayer dielectric layer. The patterned pixel electrode is formed on a part of the passivation layer and a part of the interlayer dielectric layer and contacted with a part of the passivation layer and a part of the interlayer dielectric layer. The storage capacitor includes the patterned first metal layer, a remained part of the interlayer dielectric layer located under the opening, and the patterned pixel electrode. | 12-04-2008 |
20090302330 | PHOTO DETECTOR AND METHOD FOR FORMING THEREOF - A photo detector is disclosed. The photo detector has a substrate, a semiconductor layer disposed on the substrate, an insulating layer covered on the semiconductor layer, an interlayer dielectric layer covered on the insulating layer, and two electrodes formed on a portion of the interlayer dielectric layer. The semiconductor layer has a first doping region, a second doping region, and an intrinsic region located between the first doping region and the second doping region. The interlayer dielectric layer has at least three holes to expose a portion of the insulating layer, a portion of the first doping region, and the second doping region. The electrodes are connected to the first doping region and the second doping region through two of the holes. | 12-10-2009 |
20100176890 | System and Method for Characterizing Process Variations - A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively. | 07-15-2010 |
20100253382 | System and Method for Observing Threshold Voltage Variations - A system and method for observing threshold voltage variations are provided. A ring oscillator circuit comprises a plurality of inverters arranged in a sequential loop, a plurality of test circuits having devices under test, each coupled between a respective one of the inverters and a power supply. Each test circuit has a bypass field effect transistor (FET) having a first channel coupled between the power supply and a respective one of the inverters responsive to an individual enable signal, and a FET device under test having a second channel arranged in parallel to the first channel. A method is described for determining the threshold voltage of the device under test by disabling, for one of the inverters in the ring oscillator, the first FET device such that the device under test is coupled between the power supply and the respective inverter and affects the operating frequency of the ring oscillator. | 10-07-2010 |
Patent application number | Description | Published |
20080203395 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a method for manufacturing the same are provided. First, a transparent substrate is provided. Next, a light-shielding layer is formed over the transparent substrate and a first buffer layer is formed to cover the light-shielding layer. A semiconductor layer is formed over the first buffer layer. Then, the light-shielding layer, the first buffer layer and the semiconductor layer are patterned to form a laminate pattern. A channel and a source/drain region at two sides of the channel are formed within the semiconductor layer. Then, a gate insulating layer is formed over the transparent substrate to cover the laminate pattern. A gate electrode is formed on the gate insulating layer above the channel. | 08-28-2008 |
20080283923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost. | 11-20-2008 |
20090001377 | PIXEL STRUCTURE AND FABRICATION METHOD THEREOF - A pixel structure and a fabrication method thereof are provided, wherein a semiconductor pattern and a data line are defined simultaneously by performing a half-tone or grey-tone masking process. In addition, a self-alignment manner is further adopted to fabricate a lightly doped region with symmetric lengths on two sides of a channel region through steps such as photoresist ashing and etching, so as to prevent the problem of misalignment of mask generated when a mask is used to define the lightly doped region in the conventional art. Furthermore, a source pattern and a drain pattern are made to directly contact a source region and a drain region of the semiconductor pattern, such that a process of fabricating a via is omitted. Besides, in the present invention, a common line pattern surrounding the peripheral of the pixel region is also formed to improve the aperture ratio of the pixel structure. | 01-01-2009 |
20100233859 | FABRICATION METHOD OF PIXEL STRUCTURE - A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer. | 09-16-2010 |
Patent application number | Description | Published |
20080254640 | METHOD OF REMOVING MATERIAL LAYER AND REMNANT METAL - A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved. | 10-16-2008 |
20080305600 | METHOD AND APPARATUS FOR FABRICATING HIGH TENSILE STRESS FILM - A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature. | 12-11-2008 |
20090191714 | Method of removing oxides - The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process. | 07-30-2009 |
20100001317 | CMOS TRANSISTOR AND THE METHOD FOR MANUFACTURING THE SAME - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion. | 01-07-2010 |
20100035401 | METHOD FOR FABRICATING MOS TRANSISTORS - A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer. | 02-11-2010 |
20110127589 | SEMICONDUCTOR STRUCTURE HAIVNG A METAL GATE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening. | 06-02-2011 |
20110266596 | Semiconductor device and method of making the same - In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a Ni | 11-03-2011 |
20120088345 | METHOD OF FORMING SILICIDE FOR CONTACT PLUGS - A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide. | 04-12-2012 |
20140038374 | METHOD FOR MANUFACTURING CMOS TRANSISTOR - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion. | 02-06-2014 |
Patent application number | Description | Published |
20090323559 | Method for predicting a port number of a NAT equipment based on results of inquiring the STUN server twice - We propose a method for predicting a port number of a NAT equipment according to results of inquiring a STUN server twice in this invention. A network terminal device A in a private network sends an inquiry packet to the STUN server before and after sending a hole punching request, acquires two endpoint mappings of the NAT equipment used respectively in the two inquiries from the STUN server, and delivers the endpoint mappings to another network terminal device B in another private network through a SIP server. The network terminal device B predicts a range of port numbers of the NAT equipment probably used when the hole punching request was sent, according to the endpoint mappings and a port differential of the NAT equipment, and sends packets to the predicted port numbers sequentially until a response packet is received from the network terminal device A. Hence, a connection channel is established. | 12-31-2009 |
20120134532 | ABNORMAL BEHAVIOR DETECTION SYSTEM AND METHOD USING AUTOMATIC CLASSIFICATION OF MULTIPLE FEATURES - Described herein are a system and a method for abnormal behavior detection using automatic classification of multiple features. Features from various sources, including those extracted from camera input through digital image analysis, are used as input to machine learning algorithms. These algorithms group the features and produce models of normal and abnormal behaviors. Outlying behaviors, such as those identified by their lower frequency, are deemed abnormal. Human supervision may optionally be employed to ensure the accuracy of the models. Once created, these models can be used to automatically classify features as normal or abnormal. This invention is suitable for use in the automatic detection of abnormal traffic behavior such as running of red lights, driving in the wrong lane, or driving against traffic regulations. | 05-31-2012 |
20120148092 | AUTOMATIC TRAFFIC VIOLATION DETECTION SYSTEM AND METHOD OF THE SAME - Disclosed herein are a system and method for the automatic detection of traffic and parking violations. Camera input is digitally analyzed for vehicle type and location. This information is then processed against local traffic and parking regulations to detect violations. Detectable driving offenses include, but are not limited to: no scooters, buses only, and scooters only lane violations. Detectable parking offenses include, but are not limited to: parking or loitering in bus stops, parking next to fire hydrants, and parking in no-parking zones. Camera input, detected vehicle information, and violations can be stored for later search and retrieval. The system may be configured to signal the authorities or other automated analysis systems about specific violations. When coupled with automatic license plate recognition, vehicles may be automatically matched against a registration database and reported or ticketed. | 06-14-2012 |
Patent application number | Description | Published |
20080224232 | SILICIDATION PROCESS FOR MOS TRANSISTOR AND TRANSISTOR STRUCTURE - A silicidation process for a MOS transistor and a resulting transistor structure are described. The MOS transistor includes a silicon substrate, a gate dielectric layer, a silicon gate, a cap layer on the silicon gate, a spacer on the sidewalls of the silicon gate and the cap layer, and S/D regions in the substrate beside the silicon gate. The process includes forming a metal silicide layer on the S/D regions, utilizing plasma of a reactive gas to react a surface layer of the metal silicide layer into a passivation layer, removing the cap layer and then reacting the silicon gate into a fully silicided gate. | 09-18-2008 |
20090061623 | METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE - A method of forming an electrical connection structure is described. A dielectric layer is formed covering a first conductor on a substrate, and then an opening is formed in the dielectric layer exposing the first conductor. A first cleaning step is conducted using fluorine-containing plasma to clean the surfaces of the dielectric layer and the exposed first conductor, and then at least one low-temperature annealing step is conducted. A second cleaning step is conducted using argon plasma to clean the above surfaces. A second conductor is then formed in the opening. | 03-05-2009 |
20090090395 | METHOD OF REMOVING PARTICLES FROM WAFER - A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed. | 04-09-2009 |
20090155999 | METHOD FOR FABRICATING METAL SILICIDE - A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy. | 06-18-2009 |
Patent application number | Description | Published |
20120025320 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF - A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain. | 02-02-2012 |
20120305910 | HYBRID THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL HAVING THE SAME - A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer. | 12-06-2012 |
20140087525 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF - A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain. | 03-27-2014 |
Patent application number | Description | Published |
20120181635 | Semiconductor device - In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a Ni | 07-19-2012 |
20120244669 | Method of Manufacturing Semiconductor Device Having Metal Gates - The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench. | 09-27-2012 |
20120256275 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench. | 10-11-2012 |
20130014779 | CLEANING METHOD OF SEMICONDUCTOR MANUFACTURING PROCESSAANM CHEN; Yi-WeiAACI Taichung CityAACO TWAAGP CHEN; Yi-Wei Taichung City TWAANM TSAI; Teng-ChunAACI Tainan CityAACO TWAAGP TSAI; Teng-Chun Tainan City TWAANM LAI; Kuo-ChihAACI Tainan CityAACO TWAAGP LAI; Kuo-Chih Tainan City TWAANM HUANG; Shu-MinAACI Tainan CityAACO TWAAGP HUANG; Shu-Min Tainan City TW - A cleaning method of a semiconductor manufacturing process is provided. The cleaning method is applied to a semiconductor component including a plurality of material layers formed thereon. An opening is defined in the material layers, and a side wall is exposed from the opening The side wall at least includes a first material layer and a second material layer. At first, a first cleaning process is performed till a lateral etched thickness of the first material layer is equal to a lateral etched thickness of the second material layer. Then, a byproduct formed in the first cleaning process is removed. | 01-17-2013 |
20130193577 | STRUCTURE OF ELECTRICAL CONTACT AND FABRICATION METHOD THEREOF - A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed. | 08-01-2013 |
20130257564 | POWER LINE FILTER FOR MULTIDIMENSIONAL INTEGRATED CIRCUITS - An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer. | 10-03-2013 |
20140131804 | SEMICONDUCTOR STRUCTURE - The present invention provides a semiconductor structure, comprising at least two gate electrodes disposed on a substrate, wherein each gate electrode is mushroom-shaped and respectively has a salicide region on a top of the gate electrode, wherein the width of the salicide region is larger than the width of the gate electrode. A recess is disposed between each gate electrode, wherein the recess has a recess extension disposed under the salicide region. A spacer fills the extension of the recess, wherein the profile of each gate electrode is a tapered surface, and a contact etching stop layer (CESL) covers the gate electrodes. | 05-15-2014 |
20140191298 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer. | 07-10-2014 |
20150017777 | METHOD OF FABRICATING MOS DEVICE - Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress form the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate. | 01-15-2015 |