Patent application number | Description | Published |
20080243748 | Rule set partitioning based packet classification method for Internet - The present invention provides a rule set partitioning based packet classification method for Internet. The method comprising: performing Horizontal Cut for the rule set, determining the field for partitioning a rule layer based on a target algorithm and selecting the partition manner of the Horizontal Cut, performing Horizontal Cut according to the selected partition manner of the Horizontal Cut, thereby obtaining more than one rule layers, each rule layer being a Horizontal subset, combining the rule layers to obtain a plurality of Horizontal subsets according to the total number of the pre-designated Horizontal subsets and a predefined principle, wherein the total number of said combined plurality of Horizontal subsets equals to the total number of said pre-designated Horizontal subsets; performing Vertical Cut in each of the Horizontal subsets; then forming a Hash table that can index the Vertical subsets, so that it can be used in a lookup; and realizing rule storage in each Vertical subset respectively according to the target algorithm. | 10-02-2008 |
20080273461 | Network system, traffic balancing method, network monitoring device and host - A traffic balancing system, traffic balancing device and traffic balancing method that converts IP packets by switching IP address of the destination host between the dual stack hosts communicating with each other, in order to control traffic balancing in the networks. | 11-06-2008 |
20080288691 | METHOD AND APPARATUS OF LOCK TRANSACTIONS PROCESSING IN SINGLE OR MULTI-CORE PROCESSOR - The present invention relates to a method and apparatus of lock transactions processing in a single or multi-core processor. An embodiment of the present invention is a processor with one or more processing cores, an address arbitrator, where one or more processing cores are configured to submit a lock transaction request to the address arbitrator corresponding to a specific instruction in response to the execution of the specific instruction. The lock transaction request includes a lock variable address asserted on an address bus. The processor further includes a lock controller for performing lock transaction processing in response to the lock transaction request, and notifying processing result to the processing core from which the lock transaction request was sent. The processor further includes a switching device, coupled to the address arbitrator and the lock controller, for identifying the lock transaction request and notifying the lock transaction request to the lock controller. | 11-20-2008 |
20090019290 | METHOD AND CENTRAL PROCESSING UNIT FOR PROCESSING ENCRYPTED SOFTWARE - The present invention provides a central processing unit for processing at least one encrypted software. The encrypted software comprises at least one encrypted software section. The encrypted software section is encrypted with a management key MK, and the MK being encrypted with a device key DK as a encrypted MK. The central processing unit comprises processing and cache unit, and cryptographic unit. The cryptographic unit comprises device key storage unit for storing the DK, a plurality of management key storage units for storing MKs, wherein each management key storage unit corresponding to a management key index MKI, and decryption unit. The decryption unit decrypts a encrypted MK with the DK to obtain a MK, stores the MK to a management key storage unit, and output a MKI corresponding to the management key storage unit, thus the MKI is used to correspond to the encrypted software section. Wherein, the decryption unit invokes corresponding MK according to the MKI and decrypts the encrypted software section, and directly transfers the decrypted software code and/or data to the processing and cache unit. | 01-15-2009 |
20090157900 | Method For Ipv4 Application Transition Over Ipv6 Networks - A network system adopting a first IP protocol is provided. The network system includes an address allocating server and a communication terminal supporting both the first IP protocol and a second IP protocol, wherein the address allocating server dynamically allocates an address of the second IP protocol to the communication terminal. The communication terminal includes a dynamic address manager for acquiring the dynamically allocated address of the second IP protocol of the communication terminal from the address allocating server and a second IP protocol address of the destination of a second IP protocol packet from a second IP protocol application, and an address adapter for encapsulating the second IP protocol packet from the second IP protocol application into a first IP protocol packet, wherein the second IP protocol address of the communication terminal in the header of the second IP protocol packet and the second IP protocol address of the destination are encapsulated into the first IP protocol packet. | 06-18-2009 |
20090178054 | CONCOMITANCE SCHEDULING COMMENSAL THREADS IN A MULTI-THREADING COMPUTER SYSTEM - A method and an apparatus for concomitance scheduling a work thread and assistant threads associated with the work thread in a multi-threading processor system. The method includes: searching one or more assistant threads associated with the running of the work thread when preparing to run/schedule the work thread; running the one or more assistant threads that are searched; and running the work thread after all of the one or more assistant threads associated with the running of the work thread have run. | 07-09-2009 |
20090193319 | DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD - The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme. | 07-30-2009 |
20090193424 | METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR AND CORRESPONDING PROCESSOR - The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload. | 07-30-2009 |
20090248934 | INTERRUPT DISPATCHING METHOD IN MULTI-CORE ENVIRONMENT AND MULTI-CORE PROCESSOR - Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor. | 10-01-2009 |
20100217945 | FAST CONTEXT SAVE IN TRANSACTIONAL MEMORY - The present invention provides a method, apparatus and article of manufacture, for fast context saving in transactional memory. The method creates a mapping table that includes entries corresponding to architectural registers. Each entry includes a physical register index and shadow bit of a first physical register mapped to an architectural register. In response to a detection that an update occurs to an architectural register in a transaction and its shadow bit being an invalid value, the method sets the shadow bit to be a valid value and sets a shadow register for the architectural register using the physical register index of the first physical register. The method maps a second physical register to the shadow register in order to save a modified value generated by an update process and saves the original value before the update process by use of the first physical register corresponding to the architecture register. | 08-26-2010 |
20120005678 | ACCELERATOR AND ITS METHOD FOR REALIZING SUPPORTING VIRTUAL MACHINE MIGRATION - A computer-implemented method, an accelerator hardware unit, and an article of manufacture for supporting virtual machine migration. The method includes: acquiring a task request from a task queue of an accelerator hardware unit; extracting identification information of a related virtual machine from the task request; determining whether the identification information of the related virtual machine matches the identification information of a virtual machine to be migrated, where the identification information of a virtual machine to be migrated is recorded in a virtual machine identification information table; and deleting the task request from the task queue if the extracted identification information matches the identification information of a virtual machine to be migrated. | 01-05-2012 |
20120030543 | PROTECTION OF APPLICATION IN MEMORY - A method, a memory controller and a processor architecture for protecting an application in a memory are disclosed. The application is cached as memory lines according to a size of a cache line. For example, the method comprises: in response to a load access request from a processor, reading from the memory a flagged memory line and an ECC checksum corresponding to the memory line, wherein the flagged memory line is obtained by performing a logic operation on a predetermined bit of the memory line and a flag bit for identifying the memory line; performing an ECC check on the flagged memory line by using the ECC checksum to obtain a value of the flag bit of the memory line; restoring the flagged memory line to the memory line according to the value of the flag bit; and determining whether or not to load the memory line according to the value of the flag bit and the type of the load access request from the processor. | 02-02-2012 |
20120204082 | DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD - The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme. | 08-09-2012 |
20120210106 | METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR - The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload. | 08-16-2012 |
20120288088 | METHOD AND SYSTEM FOR COMPRESSING AND ENCRYPTING DATA - A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of the original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Various embodiments improve the efficiency of the process of compression and encryption to a great extent by encrypting only the literal portion of the compression result. | 11-15-2012 |
20130010949 | METHOD AND SYSTEM FOR COMPRESSING AND ENCRYPTING DATA - A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of said original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Embodiments of the present invention improve the efficiency of the process of compression +encryption to a great extent by means of encrypting only the literal portion of the compression result. | 01-10-2013 |
20130031553 | HARDWARE ACCELERATION - Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly. | 01-31-2013 |
20130031554 | HARDWARE ACCELERATION - Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread. | 01-31-2013 |
20130136123 | METHOD AND APPARATUS FOR IMPLEMENTING A FLEXIBLE VIRTUAL LOCAL AREA NETWORK - A method and apparatus for implementing a virtual local area network. The method includes determining a global virtual local area network for transmitting a data frame in response to receiving the data frame at a first switch, encapsulating the data frame based at least in part on said determination and transmitting it to at least one second switch over the determined global virtual local area network. The data frame is received at the second switch and an identifier of the global virtual local area network is obtained according to the data frame. Based at least in part on the identifier of the global virtual local area network, it is determined that which local virtual local area network served by the second switch the de-capsulated data frame can be sent to. | 05-30-2013 |
20130185474 | TECHNIQUES USED BY A VIRTUAL MACHINE IN COMMUNICATION WITH AN EXTERNAL MACHINE AND RELATED VIRTUAL MACHINE SYSTEM - A method used by a virtual machine in communication with an external machine includes providing a single sharing page that is shared between a plurality of virtual machines and a particular virtual machine, wherein the particular virtual machine and the plurality of virtual machines run on a same physical machine; writing into the single sharing page a data packet to be sent by the virtual machine to the external machine; scheduling a page swap between the single sharing page and a blank memory page of the particular virtual machine; and sending, to the external machine, the data packet in the memory page of the particular virtual machine subsequent to the page swap. | 07-18-2013 |
20130290305 | DATA FILTERING IN THE INTERNET OF THINGS - This invention relates to the Internet of Things (IOT), and discloses a method and apparatus of data filtering in the IOT, where the IOT includes a plurality of sensor devices. The method includes: inputting an application deployed rule; converting the rule into at least one sub-predicate expression having static predicates and dynamic predicates; inputting data collected by the sensor devices; matching the collected data with the static predicates and the dynamic predicates of the sub-predicate expression in sequence; and distributing matched data to the application. In this invention, a rule is divided into static and dynamic predicates, and a match is performed on static predicates before dynamic predicates, so that the speed of predicate match can be improved and fast and efficient data filtering in the IOT can be achieved. | 10-31-2013 |
20140040555 | DATA PROCESSING, METHOD, DEVICE, AND SYSTEM FOR PROCESSING REQUESTS IN A MULTI-CORE SYSTEM - The present disclosure provides a method, device, and system for processing a request in a multi-core system. The method comprises steps of: receiving a request for data by a filter from a requesting unit; comparing an indicator indicative of a logical partition in the request with an indicator indicative of the logical partition in a record of the filter; searching in a unit where the filter is located based on the request and returning a search result to the requesting unit if a comparison result matches; and returning a NONE response to the requesting unit from the filter if the comparison result does not match. | 02-06-2014 |
20140379956 | MANAGING A TRANSLATION LOOKASIDE BUFFER - Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present invention, a series of operations caused by TLB miss would not need intervening from the hypervisor. On the contrary, when a TLB miss occurs, the hardware directly issues an interrupt to a virtual machine. In this way, the TLB can be efficiently managed by means of a hardware-level auxiliary translation table. Therefore, system overheads can be greatly reduced and system performance can be improved. Methods and apparatuses associated with hardware, hypervisor, and virtual machine in a virtualization enabled system are disclosed, respectively. | 12-25-2014 |