Patent application number | Description | Published |
20120136858 | Method to Coordinate Data Collection Among Multiple System Components - A method, computer program product and computer system for coordinating data collection from a component of a data processing system is disclosed. The component registers with a dispatcher, wherein the component is a computer resource of the data processing system and is configured to accept at least one query, and the registration comprising data types handled by the at least one component, wherein the dispatcher is allocated computer resources of the data processing system. The component receives from the dispatcher a notification to perform the query against specified data structures, wherein the query comprises an action. The component, responsive to receiving notification, determines whether data structures of a data type specified in the query are handled. The data processing system runs the query to determine whether the query is satisfied. The data processing system executes the action. | 05-31-2012 |
20130055215 | CAPTURING MULTI-COMPONENT TRACE FOR UNIT FOR WORK - Provided are techniques for the tracing of computer processes and, more specifically, to techniques that enable a work unit to be traced across multiple processing components. A data structure is created and associated with a work unit. The first time a unit of work is processed a tracing context is retrieved form a pool and associated with the data structure. As the unit of work is passed from component to component, the data structure is passed so that each component has access and is able to augment the same tracing context associated with the unit of work. | 02-28-2013 |
20140089341 | COORDINATING DATA COLLECTION AMONG SYSTEM COMPONENTS - A method, computer program product and computer system for coordinating data collection from a component of a data processing system is disclosed. The component registers with a dispatcher, wherein the component is a computer resource of the data processing system and is configured to accept at least one query, and the registration comprising data types handled by the at least one component, wherein the dispatcher is allocated computer resources of the data processing system. The component receives from the dispatcher a notification to perform the query against specified data structures, wherein the query comprises an action. The component, responsive to receiving notification, determines whether data structures of a data type specified in the query are handled. The data processing system runs the query to determine whether the query is satisfied. The data processing system executes the action. | 03-27-2014 |
20140181795 | CAPTURING MULTI-COMPONENT TRACE FOR UNIT OF WORK - Provided are techniques for the tracing of computer processes and, more specifically, to techniques that enable a work unit to be traced across multiple processing components. A data structure is created and associated with a work unit. The first time a unit of work is processed a tracing context is retrieved form a pool and associated with the data structure. As the unit of work is passed from component to component, the data structure is passed so that each component has access and is able to augment the same tracing context associated with the unit of work. | 06-26-2014 |
Patent application number | Description | Published |
20090103391 | Memory clock generator having multiple clock modes - An integrated circuit | 04-23-2009 |
20090129194 | Access collision within a multiport memory - A multiport memory | 05-21-2009 |
20100195365 | ROM array - A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design. | 08-05-2010 |
20100329044 | Assisting write operations to data storage cells - A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal. | 12-30-2010 |
20110072323 | Supporting scan functions within memories - A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch. | 03-24-2011 |
20110122712 | Controlling voltage levels applied to access devices when accessing storage cells in a memory - A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line. | 05-26-2011 |
20110149674 | Integrated circuit memory with word line driving helper circuits - An integrated circuit memory | 06-23-2011 |
20110187438 | Reducing current leakage in a semiconductor device - An integrated circuit, method of controlling power supplied to semiconductor devices, a method of designing an integrated circuit and a computer program product are disclosed. The integrated circuit comprises: a semiconductor device for handling data; a power source for powering said semiconductor device, said power source comprising a high voltage source for supplying a high voltage level and a low voltage source for supplying a low voltage level; a plurality of switching devices arranged between at least one of the high or low voltage sources and the semiconductor device. There is also a control device for controlling a first set of the plurality of switching devices to connect one of the high or low voltage sources to the semiconductor device and for controlling a second set of the plurality of switching devices to connect the one of the high or low voltage sources to the semiconductor device. At least some of the first set of the plurality of switching devices have a higher resistance when closed and providing a connection than at least some of the second set of the plurality of switching devices such that when the first set of the plurality of switching devices connect the semiconductor device to the one of the voltage sources the semiconductor device operates with a lower performance than when the second set of the plurality of switching devices connect the semiconductor device to the one of said voltage sources. | 08-04-2011 |
20110314317 | Power supply detection circuitry and method - When switching a power supply rail for a processing circuit from a first voltage level to a second voltage level, power level detection circuitry detects when the supply voltage level reaches a predetermined voltage level. The power level detection circuitry comprises a first transistor and a second transistor which compete with one another such that the first transistor pulls a signal node voltage level at a signal node towards the supply voltage level while the second transistor pulls the signal node voltage level towards an external power supply voltage level. When the supply voltage level on the power supply rail reaches the predetermined voltage level, the first transistor overcomes the second transistor to trigger a ready signal indicating that the supply voltage level has reached the predetermined voltage level. | 12-22-2011 |
20120002499 | Power control of an integrated circuit memory - An integrated circuit memory | 01-05-2012 |
20120320694 | Write assist in a dual write line semiconductor memory - A semiconductor memory storage device is disclosed, the memory having a plurality of storage cells. Each storage cell comprises two access control devices, each of the access control devices providing the storage cell with access to or isolation from a respective one of two data lines in response to an access control signal, the two data lines being connected to one data port; access control circuitry for applying the access control signal via one of two access control lines to control a plurality of the access control devices; wherein one of the two access control devices of each storage cell is controlled by the access control signal received from a first of the two access control lines to provide the storage cell with access to or isolation from a first of the two data lines, and one further of the two access control devices is controlled by the access control signal received from a second of the two access control lines to provide the storage cell with access to or isolation from a second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines. In some cases the access control signal is applied to the second of the two access control lines a predetermined time after it is applied to the first of the two access control lines. | 12-20-2012 |
20130182484 | WORD LINE AND POWER CONDUCTOR WITHIN A METAL LAYER OF A MEMORY CELL - A memory cell | 07-18-2013 |
20140115554 | METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE - A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler. | 04-24-2014 |
20140247081 | COMBINATORIAL CIRCUIT AND METHOD OF OPERATION OF SUCH A COMBINATORIAL CIRCUIT - An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching. | 09-04-2014 |
20140250278 | INTEGRATED LEVEL SHIFTING LATCH CIRCUIT AND METHOD OF OPERATION OF SUCH A LATCH CIRCUIT - An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry. | 09-04-2014 |
20140269091 | MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH A MEMORY DEVICE - A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell. | 09-18-2014 |
20150085586 | MEMORY DEVICE AND METHOD OF OPERATION OF SUCH A MEMORY DEVICE - A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells. | 03-26-2015 |
Patent application number | Description | Published |
20110307848 | METHOD FOR PREPARING FOR AND FORMALLY VERIFYING A MODIFIED INTEGRATED CIRCUIT DESIGN - A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity. | 12-15-2011 |
20120192132 | METHOD FOR MANIPULATING AND REPARTITIONING A HIERARCHICAL INTEGRATED CIRCUIT DESIGN - A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances. | 07-26-2012 |
20120239717 | FUNNEL SHIFTER IMPLEMENTATION - A funnel shifter includes an input, an output, and a multiplexer unit including a number of multiplexer levels. The multiplexer unit may perform one of a plurality of shift operations on an input value and to provide an output value in response to receiving a shift value and a shift operation value. A first multiplexer level may be configured to format and expand the input value into a larger intermediate value. At least a second multiplexer level may be configured to perform a linear shift of the intermediate value without wrapping any bits for creating the output value. At least some of the multiplexer levels may include multiplexer select signals that may be represented as a plurality of N-Nary one of N signals where N is greater than or equal to two, wherein each of the plurality of N-Nary signals being implemented on a set of physical wires. | 09-20-2012 |
Patent application number | Description | Published |
20080209178 | Method and Apparatus for Back to Back Issue of Dependent Instructions in an Out of Order Issue Queue - A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set. | 08-28-2008 |
20080256345 | Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System - An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions. | 10-16-2008 |
20080294884 | Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors - A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread. | 11-27-2008 |
20090150657 | Method and Apparatus for Inhibiting Fetch Throttling When a Processor Encounters a Low Confidence Branch Instruction in an Information Handling System - An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. | 06-11-2009 |
20090177858 | Method and Apparatus for Controlling Memory Array Gating when a Processor Executes a Low Confidence Branch Instruction in an Information Handling System - An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely. | 07-09-2009 |
20090193231 | METHOD AND APPARATUS FOR THREAD PRIORITY CONTROL IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible. | 07-30-2009 |
20090193240 | METHOD AND APPARATUS FOR INCREASING THREAD PRIORITY IN RESPONSE TO FLUSH INFORMATION IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction. In this manner, a fetcher in the processor obtains ready access to the particular thread in the memory array. | 07-30-2009 |