Yeong
Kay K. Yeong, Hertfordshire GB
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20100098952 | METHOD, PRINTING DEVICE, AND FORMULATIONS FOR DECORATING GLASS OR CERAMIC ITEMS - A method and a printing device ( | 04-22-2010 |
Lester Yeong, Singapore SG
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20100136273 | REACTIVELY-COUPLED ARTICLES AND RELATED METHODS - The present invention is an article of construction formed from an article adhesively-bonded to a layering material through (a) reactive coupling of a functionalized nitroxide or (b) the adhesion of components in a polymer matrix made from or containing a polymer, an organic peroxide, and a functionalized nitroxide. The initial article may be expanded. It may also be polar or nonpolar. Similarly, the layering material may be polar or nonpolar. Other embodiments of the present invention are described, including other articles and methods for preparing the articles. The useful articles of the present invention include shoe outsoles and midsoles, paints, overmolded articles, weather stripping, gaskets, profiles, belts, hoses, tubes, durable goods, tires, construction panels, leisure and sports equipment foams, energy management foams, acoustic management foams, insulation foams, other foams, automotive parts (including bumper fascias, vertical panels, soft thermoplastic polyolefin skins, and interior trim), toys, supported films (including single-ply and co-extruded films), glass laminations, leather articles (synthetic and natural), personal health care and hygiene articles, other metal laminates, wood composites, automotive belts, hoses, tubes, conveyor belts, footwear, sporting goods, and filled articles. | 06-03-2010 |
Sai Hooi Yeong, Singapore SG
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20090087971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION DIFFUSION - A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling. | 04-02-2009 |
20090286373 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH SHALLOW DIFFUSION REGIONS - A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth. | 11-19-2009 |
20100124809 | METHOD FOR FORMING A SHALLOW JUNCTION REGION USING DEFECT ENGINEERING AND LASER ANNEALING - A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device. | 05-20-2010 |
20110034040 | LOCALIZED ANNEAL - A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed. | 02-10-2011 |
20120009749 | METHOD FOR FABRICATING NANO DEVICES - Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire. | 01-12-2012 |
20120034745 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION DIFFUSION - A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling. | 02-09-2012 |
20120070971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions. | 03-22-2012 |
Sai-Hooi Yeong, Zhubei City TW
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20160111334 | FINFET FORMATION PROCESS AND STRUCTURE - A FinFET and methods for forming a FinFET are disclosed. In a method, first trenches are formed in a substrate. First isolation regions are then formed in the first trenches. An epitaxial region is epitaxially grown between the first isolation regions. A second trench is formed by etching in the epitaxial region, forming a plurality of fins. A second isolation region is formed in the second trench. A structure includes a substrate, a first fin on the substrate, a gate dielectric over the first fin, and a gate electrode over the gate dielectric. The first fin comprises an epitaxial layer having a stacking fault defect density less than 1*10 | 04-21-2016 |
Sai-Hooi Yeong, Hsinchu County TW
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20150294897 | STRUCTURES AND METHODS FOR FORMING FIN STRUCTURES - Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices. | 10-15-2015 |
20160056295 | FinFET Transistor with U-Shaped Channel - A semiconductor device having a u-shaped FinFET and methods of forming the same are disclosed. The semiconductor device includes a substrate and a fin over the substrate, wherein the fin has a u-shape from a top view with first and second arm portions and a bridge portion connecting the first and second arm portions. The semiconductor device further includes a first gate over the substrate, engaging the fin at both the first and second arm portions and the bridge portion. A source region of the FinFET is formed in the first arm portion, a drain region of the FinFET is formed in the second arm portion, and a channel region of the FinFET is formed in the fin between the source region and the drain region. | 02-25-2016 |
Ya Chee Yeong, Singapore SG
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20130234697 | METHOD AND DEVICE FOR COUNTING ENERGISATION EVENTS - A method and a device for counting energisation events. The device comprises a connector member for connecting to an energisable element; a sampling module coupled to the connector member, the sampling module configured to detect energisation of the energisable element; a count module coupled to the sampling module, the count module configured to count a number of detected energisation events of the energisable element. | 09-12-2013 |
20130249316 | Automatic Configurable Relay - An automatic configurable relay and a method for automatically configuring a relay. The relay comprises an input sampling module for coupling to a source to be monitored, the sampling module configured to detect a first value of a parameter of the source to be monitored; and a processing module configured to set a working condition based on the detected first value. | 09-26-2013 |
20140070953 | RELAY AND A METHOD FOR INDICATING A RELAY FAILURE - A relay and a method for indicating a relay failure may be provided, whereby the relay comprises a switch assembly capable of providing a trigger signal based on a switching status; an energisation element capable of energisation to affect the switch assembly; and a light indication for indicating a switching status of the switch assembly. | 03-13-2014 |
Yoon Yeong, Thousand Oaks, CA US
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20120068897 | ANTENNA SYSTEM AND FILTER - Antenna systems and antenna filters are provided, for example for use in a windshield or on a roof of a vehicle. An antenna system comprises a first antenna, a second antenna, and a filter. The first antenna is configured to operate at a first frequency. The second antenna is configured to operate at a second frequency. The filter is coupled to the first antenna. The filter is configured to create an open circuit condition at the second frequency and reduce secondary radiation between the first and second antennas. | 03-22-2012 |