Yeh, Hsinchu Hsien
Chao-Chi Yeh, Hsinchu Hsien TW
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20100302133 | Apparatus for Controlling a Display and Method Thereof - An apparatus for controlling a display having a backlight module provided with a first set of units and a display panel provided with a second set of units is provided. In one embodiment, the apparatus comprises a reference value generator, a control value generator, and a compensation circuit. The reference value generator generates a reference value representative of a portion of pixels contained in an input image associated with one of the second set of units. The control value generator generates a control value to control one of the first set of units in view of the reference value. The compensation circuit adjusts the portion of pixels contained in the input image in view of the control value. The one of the first units is associated with the one of the second units. | 12-02-2010 |
Chun Wen Yeh, Hsinchu Hsien TW
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20110001768 | Display Controller, Video Signal Transmitting Method and System - A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted. | 01-06-2011 |
20120025894 | Multi-Mode Output Transmitter - A multi-mode output transmitter includes a pair of driving circuits and a pair of common circuits. Each of the driving circuits includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and each of the common circuits includes a p-channel MOSFET. In one transmission mode, one of the pair of common circuits and one of the pair of driving circuits complementarily conduct; and in another transmission mode, the pair of common circuits simultaneously conduct to provide termination resistors. | 02-02-2012 |
20120057262 | Low Voltage Transmitter with High Output Voltage - A transmitter comprises a protection circuit; a first termination resistor having a first end coupled to a first voltage source, and a second end coupled to the protection circuit; a second termination resistor having a first end coupled to the first voltage source, and a second end coupled to the protection circuit, wherein the second end of the first termination resistor and the second end of the second termination resistor form a differential output pair; a current switch coupled to the protection circuit; a current source coupled to the current switch; and a pre-driver circuit coupled to the current switch, for controlling the current switch, making the differential output pair generate an output current. Wherein, the pre-driver circuit receives a second voltage source, and the first voltage source is higher than the second voltage source. | 03-08-2012 |
Chwei-Jing Yeh, Hsinchu Hsien TW
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20110013339 | ASSEMBLY OF MAGNETIC CAPACITOR WITH PACKAGING - An assembly of an magnetic capacitor with a packaging comprises: a magnetic capacitor; two packing electrodes, one of the two end electrodes including an upper magnetic casing installed upon a top surface of the capacitor and a lower magnetic casing installed at a lower surface of the capacitor; each of the upper magnetic casing and the lower magnetic casing being formed with extruding pieces which is arranged around a lateral side of the capacitor; and at least one insulation material for isolating magnetic material is arranged within the magnetic capacitor. | 01-20-2011 |
Ellen Chen Yeh, Hsinchu Hsien TW
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20090243679 | Semi-Digital Delay Locked Loop Circuit and Method - A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal. | 10-01-2009 |
Jui-Hua Yeh, Hsinchu Hsien TW
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20110187567 | Phase Digitizing Apparatus and Method Thereof - A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit. | 08-04-2011 |
20110188600 | Sequence Transition Point Determining Method and Apparatus Thereof - A determining method and apparatus thereof for a transition point of a sequence which can be applied to a decoder. The determining method determines the transition point of the sequence having N numbers, wherein the sequence is composed of a first value and a second value and N is a positive integer. The determining method includes determining the position the first value appearing consecutively in the sequence to determine a first interval; determining the position the second value appearing consecutively in the sequence to determine a second interval; and determining the longer interval between the first interval and the second interval, when the first interval is longer, determining an adjacency of the first interval and the second value as the transition point according to the first interval, and when the second interval is longer, determining an adjacency of the second interval and the first value as the transition point. | 08-04-2011 |
Meng Chieh Yeh, Hsinchu Hsien TW
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20100321575 | Method for Processing On-Screen Display and Associated Embedded System - An embedded system for processing an on-screen display (OSD) includes an input apparatus, a user interface resource storage unit and a two-dimensional (2D) graphic engine. The method for processing the OSD includes receiving a control command associated with a 2D image processing procedure, the 2D image processing procedure generating a transitional image according to a first 2D image and a second 2D image, and displaying the first 2D image, the transitional image and the second 2D image to render a three-dimensional-like (3D-like) OSD. | 12-23-2010 |
Ming-Chieh Yeh, Hsinchu Hsien TW
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20110001768 | Display Controller, Video Signal Transmitting Method and System - A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted. | 01-06-2011 |
20110074520 | I/O Circuit Calibration Method and Associated Apparatus - An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end. | 03-31-2011 |
20110131354 | Apparatus and Method of Generating Universal Memory I/O - A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function. | 06-02-2011 |
20110153963 | Memory Controller and Associated Control Method - A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer. | 06-23-2011 |
20110158005 | Data Access Apparatus and Associated Method for Accessing Data Using Internally Generated Clocks - The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode. | 06-30-2011 |
20110314214 | Memory Sharing System and Memory Sharing Method - A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right. | 12-22-2011 |
Po Lin Yeh, Hsinchu Hsien TW
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20110187567 | Phase Digitizing Apparatus and Method Thereof - A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit. | 08-04-2011 |
20110188600 | Sequence Transition Point Determining Method and Apparatus Thereof - A determining method and apparatus thereof for a transition point of a sequence which can be applied to a decoder. The determining method determines the transition point of the sequence having N numbers, wherein the sequence is composed of a first value and a second value and N is a positive integer. The determining method includes determining the position the first value appearing consecutively in the sequence to determine a first interval; determining the position the second value appearing consecutively in the sequence to determine a second interval; and determining the longer interval between the first interval and the second interval, when the first interval is longer, determining an adjacency of the first interval and the second value as the transition point according to the first interval, and when the second interval is longer, determining an adjacency of the second interval and the first value as the transition point. | 08-04-2011 |
Rong-Hwei Yeh, Hsinchu Hsien TW
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20100122727 | Method for fabricating III-V compound semiconductor solar cell and structure thereof - A method for fabricating a III-V compound semiconductor solar cell includes forming a window layer made of III-V compound material over a top surface of an solar cell structure; forming a periodic array of hole textures of the window layer by using a lithography and etching process; and depositing an anti-reflection coating film to cover the window layer. A III-V compound solar cell structure is also provided to enhance the conversion efficiency of photovoltaic. | 05-20-2010 |
Ting-Hao Yeh, Hsinchu Hsien TW
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20140009437 | MUTUAL CAPACITIVE TOUCH PANEL AND TOUCH CONTROL SYSTEM - A single-layer mutual capacitive touch panel operable under control of a controller is provided. The mutual capacitive touch panel includes a first driving electrode, a second driving electrode, N number of first receiving electrodes surrounding the first driving electrode, M number of second receiving electrodes surrounding the second driving electrode, a driving channel, and (N+M) number of receiving channels. The controller simultaneously sends a driving signal to the first driving electrode and the second driving electrode via the driving channel. When sending the driving signal, the controller receives (N+M) number of sensing results via the (N+M) number of receiving channels. The N number of first receiving electrodes and the M number of second receiving electrodes correspond to different receiving channels. | 01-09-2014 |
Wen-Yung Yeh, Hsinchu Hsien TW
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20110059559 | ALTERNATING CURRENT LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF - An alternating current light-emitting device includes a substrate, a plurality of microdie light-emitting elements formed on the substrate, a rectifying element-dedicated member formed on a surface of a portion of microdie light-emitting elements, a rectifying unit formed on the rectifying element-dedicated member and provided with at least four rectifying elements forming a Wheatstone bridge circuit, and an electrically conductive structure electrically connecting the rectifying elements and the microdie light-emitting elements. With the rectifying unit being formed on the rectifying element-dedicated member, the rectifying elements are highly tolerant of reverse bias and feature low starting forward bias. Also, the present invention provides a method for fabricating an alternating current light-emitting device. | 03-10-2011 |
Yu-Min Yeh, Hsinchu Hsien TW
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20140111265 | DELAY CIRCUIT - A delay circuit for receiving an input signal and generating a delayed output signal. The delay circuit includes a first delay module and a second delay module. The first delay module includes a first delay unit for generating a first delayed signal according to an input signal and a first logic unit, coupled to the first delay unit, for generating a first delayed output signal according to the first delayed signal and the input signal. The second delay module includes a second delay unit for generating a second delayed signal according to the first delayed output signal and a second logic unit, coupled to the second delay unit, for generating the delayed output signal according to the second delayed signal and the input signal. | 04-24-2014 |