Patent application number | Description | Published |
20140347313 | ELECTROMAGNETIC INDUCTION PANEL STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND ELECTROMAGNETIC HANDWRITING INPUT DEVICE - An electromagnetic induction panel structure includes a multilayer substrate, a first cover unit and a second cover unit. The multilayer substrate includes a first outermost lateral conductive layer and a second outermost lateral conductive layer respectively disposed on two opposite outermost surfaces thereof. The first cover unit is disposed on the first outermost lateral conductive layer. The second cover unit is disposed on the second outermost lateral conductive layer. For example, the first cover unit includes a first insulating layer directly formed on the first outermost lateral conductive layer for directly contacting the first outermost lateral conductive layer. The second cover unit includes a second insulating layer directly formed on the second outermost lateral conductive layer for directly contacting the second outermost lateral conductive layer. The second cover unit includes a wave-absorbing material layer directly formed on the second insulating layer for directly contacting the second insulating layer. | 11-27-2014 |
20150015268 | ELECTROMAGNETIC INPUT DEVICE AND COIL DETECTION CIRCUIT THEREOF - A coil detection circuit thereof for an electromagnetic input device including a plurality of first loop coils and second loop coils includes a first detection unit, a second detection unit and a selection unit. When the selection unit selects one the first loop coils to emit an electromagnetic signal for each one of the second loop coils, each one of the second loop coils forms a second closed loop for receiving the electromagnetic signal, and the second detection unit detects a second signal. When one of the second loop coils forms an open circuit or short circuit, the second detection unit detects an open-circuit signal or a short-circuit signal. | 01-15-2015 |
20150116287 | ELECTROMAGNETIC WRITING UNIT AND ELECTROMAGNETIC HANDWRITING PEN FOR CONCURRENTLY PROVIDING INK WRITING AND ELECTROMAGNETIC WRITING FUNCTIONS - An electromagnetic handwriting pen includes a casing unit, an ink writing unit and an electromagnetic writing unit. The ink writing unit is disposed inside the casing unit and includes an ink pen core having a pen nib. The electromagnetic writing unit is disposed inside the casing unit and includes a circuit substrate far away from the pen nib, an electricity conducting element adjacent to the circuit substrate, an elastic element insulatively disposed between the circuit substrate and the electricity conducting element, and a magnetic structure adjacent to the pen nib and electrically connected to the circuit substrate. The circuit substrate has at least two electrode portions adjacent to and facing the electricity conducting element. Whereby, when the electricity conducting element is moved to concurrently contact the at least two electrode portions, the at least two electrode portions are electrically connected with each other through the electricity conducting element. | 04-30-2015 |
20150301628 | CIRCUIT OF FREQUENCY COUNTER AND METHOD THEREOF - A circuit of frequency counter is adapted for an electromagnetic board with an electromagnetic pen. The counter exemplarily includes a source count module, a motion count module, a logic module, a switching gate module, a signal-capturing module, a frequency-counting module and a control module. The source count module counts number of clock pulses of a first clock signal. A receiver mode is switched by the switching gate module when the number reaches a first predetermined value. The motion count module counts number of clock pulses of a second clock signal. A transmitter mode is made by the switching gate module when the number reaches a second predetermined value. When a cumulative number of circular number counted by the frequency-counting module reaches a third predetermined value, the frequency-counting module completes counting a first high-frequency clock signals, and the control module obtains an operating frequency for the electromagnetic pen. | 10-22-2015 |
Patent application number | Description | Published |
20090074403 | SELF-HEALING RING-BASED PASSIVE OPTICAL NETWORK - A self-healing ring-based passive optical network (PON) including an optical fiber ring, an optical line termination (OLT), and a plurality of optical network units (ONUs) is provided. The optical fiber ring has a first end and a second end. The OLT is coupled to the first and the second end. The OLT receives a first signal from the first end or the first and the second end and transmits a second signal to the first end or the first and the second end. Each of the ONUs has a third end and a fourth end both coupled to the optical fiber ring. Each of the ONUs receives the second signal from the third and the fourth end and transmits the first signal to the third and the fourth end. The ONUs connect to the OLT through the optical fiber ring so as to form a ring-based PON. | 03-19-2009 |
20090086787 | FIBER RING LASER - A fiber ring laser is provided, which includes an optic amplifier, a first optical coupler (OCP), a second OCP, a first fiber ring, a second fiber ring, a first polarization controller (PC), and a second PC. The first fiber ring is coupled to the optic amplifier, the first and the second OCPs. The second fiber ring is coupled to the first and the second OCPs. The optic amplifier amplifies a first laser beam with a specified wavelength range. The first fiber ring receives the first laser beam. The first and the second fiber rings respectively provide a first and a second resonant cavities. The first and the second PCs respectively control polarization states of the first and second resonant cavities. The first laser beam resonates in the first and the second resonant cavities to generate a second laser beam with a first and a second wavelengths. | 04-02-2009 |
20090110397 | PREVENTION OF COLLISION FOR TIME DIVISION MULTIPLEXING OPTICAL NETWORK, APPARATUS AND METHOD THEREOF - An apparatus for preventing collision of upstream signals is provided. The apparatus is suitable for a time division multiplexing (TDM) passive optical network (PON). The apparatus includes an optical coupler device, an optic-electron converter (O/E), a control system, and an optical signal switch module. The O/E is coupled to the optical coupler device, the control system is coupled to the O/E, and the optical signal switch module is coupled to the optical coupler device and the control system. The optical coupler device receives a first optical signal and splits the first optical signal into a second optical signal and a third optical signal. The O/E converts the second optical signal into a first electrical signal. The control system generates a control signal according to the first electrical signal. The optical signal switch module determines whether to stop the third optical signal from passing the apparatus according to the control signal. | 04-30-2009 |
20100226653 | CIRCUIT FOR SWITCHING SIGNAL PATH, ANTENNA MODULE AND RADIO OVER FIBER SYSTEM - A circuit for switching a signal path includes a path selection element, a detector, a switch, and a control circuit. A first end and a third end of the path selection element are coupled to the detector and the switch, respectively. The switch is normally in a conductive status for outputting an upload signal through the path selection element and the switch when the upload signal is input from a second end of the path selection element. When a download signal is transmitted to the detector, the detector transmits the download signal to the path selection element and enables a detection signal. The control circuit switches the switch status to an open-circuit status for outputting the download signal isolated by the switch from the second end of the path selection element. Until the download signal is transmitted completely, the control circuit switches the switch status to the conductive status. | 09-09-2010 |
20110110667 | OPTICAL NETWORK AND OPTICAL SIGNAL MODULATION METHOD THEREOF - An optical network and an optical signal modulation method thereof are provided. The optical network includes an optical fiber and a remote node (RN). The RN receives a continuous carrier wave from the optical fiber and modulates the continuous carrier wave to generate a first frequency offset carrier wave The frequency of the first frequency offset carrier wave is different from that of the continuous carrier wave. A first user device re-modulates and loads data to the first frequency offset carrier wave to generate a first upstream signal. The frequency of the first upstream signal is the same as that of the first frequency offset carrier wave. The RN inputs the first upstream signal into the optical fiber. | 05-12-2011 |
Patent application number | Description | Published |
20100149703 | ESD CLAMP CIRCUIT APPLIED TO POWER AMPLIFIER - An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided. | 06-17-2010 |
20130170082 | INTEGRATED CIRCUIT HAVING A CHARGED-DEVICE MODEL ELECTROSTATIC DISCHARGE PROTECTION MECHANISM - An integrated circuit having charged-device model (CDM) electrostatic discharge (ESD) protection includes an I/O circuit, at least one CDM ESD protection device, and at least one internal circuit. The integrated circuit further includes at least one TSV (Through Silicon Via) each being coupled between a ground of at least one ground of the input/output circuit and one of the at least one ESD protection device, wherein each of the at least one ESD protection device is coupled between one of the at least one TSV and a ground of one of the at least one internal circuit. | 07-04-2013 |
20150288172 | CIRCUIT AND METHOD FOR ELECTROSTATIC DISCHARGE CLAMPING - A circuit and a method for electrostatic discharge clamping are provided. The circuit includes a detection module, a control module, and a clamping module. The detection, control, and clamping modules are coupled with a first power line of a first power source and a second power line of the first power source. Third terminals of the detection, control and clamping modules are coupled to a first power line of a second power source, a voltage division terminal of the detection module, a fourth terminal of the control module respectively. According to an electrostatic discharge event on the first power line of the first power source, the division voltage terminal of the detection module provides a voltage to the control module. Then, the control module controls the clamping module to couple the first power line of the first power source to the second power line of the first power source. | 10-08-2015 |
Patent application number | Description | Published |
20090134903 | LOOP-BACK TESTING METHOD AND APPARATUS FOR IC - A test system for testing operability of integrated circuits includes: a first IC, for modulating a first signal to generate a first modulated signal and transmitting the first modulated signal, and for receiving a second modulated signal and demodulating the second modulated signal to generate a second signal; a first loop antenna, coupled to the first IC, for receiving the first modulated signal and sending the first modulated signal back to the first IC as the second modulated signal; and a tester circuit coupled to the first IC, for generating the first signal to the first IC, receiving the second signal from the first IC, and comparing the first signal and the second signal to determine the operability of the first IC. | 05-28-2009 |
20120056614 | Multi-State Indicator - A multi-state indicator comprises a voltage generator, for generating M voltages, with M being an integer larger than 3; and a multi-state detector, coupled to the voltage generator, for receiving M voltages, having a voltage input end for receiving an input voltage to generate an indication signal whereby the indication signal is capable of indicating the input voltage with reference to the M voltages. Unlike the prior art, a multi-state detector having level shifters according to the present invention alleviates problems of static currents and over-large areas for circuits implementing typical differential comparators. | 03-08-2012 |
20120146427 | LOW LEAKAGE IO CIRCUIT AND ASSOCIATED APPARATUS - A low-leakage IO circuit is provided. The IO circuit includes an impedance path between a pad and a power supply. The impedance path bypasses a signal path of the pad and includes a switch circuit. According to a relationship between voltages of the power supply and the pad of the IO circuit, the switch circuit selectively conducts the impedance path. When the power supply provides power normally, the switch circuit conducts the impedance path to provide a pull-up resistor between the pad and the power supply. When the power supply provides no power and its voltage is lower than a voltage of the pad, the switch circuit disconnects the conducting path to effectively reduce power leakage. | 06-14-2012 |
20150214947 | INTEGRATED CIRCUIT CAPABLE OF PREVENTING CURRENT BACKFLOW TO POWER LINE - An integrated circuit capable of preventing current backflow to a power line is provided. The integrated circuit includes an input circuit. The input circuit includes a bonding pad and a pull-up circuit, a pull-up switch, a bulk controlled switch and a control circuit. The pull-up switch includes a first control node and a first bulk node. The bulk controlled switch includes a second control node and a second bulk node. The control circuit controls the first and second control nodes according to an internal signal, a power voltage of the power line and a pad voltage of the bonding pad. When the power voltage is a predetermined voltage, the control circuit turns on the bulk controlled switch. When the power line is at a ground voltage and the bonding pad voltage is at the predetermined voltage, the control circuit turns off the bulk controlled switch and the pull-up switch. | 07-30-2015 |
Patent application number | Description | Published |
20090057554 | METHOD FOR PHOTORESIST CHARACTERIZATION AND ANALYSIS - A method for photoresist characterization includes forming a photoresist on a supportive structure; and characterizing the photoresist using a metrology tool selected from the group consisting of a transmission electron microscope (TEM), a scanning electron microscope (SEM), an atomic force microscope (AFM), a small angle X-ray scattering (SAXS) and a laser diffraction particle analyzer. | 03-05-2009 |
20090203224 | Si Device Making Method By Using A Novel Material For Packing and Unpacking Process - A method of lithography patterning includes forming a resist pattern on a substrate, the resist pattern including at least one desired opening and at least one padding opening therein on the substrate; forming a patterned photosensitive material layer on the resist pattern and the substrate, wherein the patterned photosensitive material layer covers the padding opening of the resist pattern; and applying a resolution enhancement lithography by assist of chemical shrink (RELACS) process to the desired opening of the resist pattern. | 08-13-2009 |
20140135657 | Management system and method for damage risk of tissue pressure - According to one embodiment of a management system for damage risk of tissue pressure, at least one pressure sensor is deployed on at least one pressure-withstanding location on a body surface of a user, and detects a plurality of extremity pressure signals from the at least a pressure-withstanding location. An information processing device uses the plurality of extremity pressure signals to compute and store at least one risk assessment index, uses a plurality of features of the plurality of extremity pressure signals to compute at least one risk adjustment factor, and then uses the at least one risk adjustment factor to calibrate the at least one risk assessment index. | 05-15-2014 |
Patent application number | Description | Published |
20120221766 | FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF - A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal. | 08-30-2012 |
20120246384 | FLASH MEMORY AND FLASH MEMORY ACCESSING METHOD - A flash memory accessing method is provided. The method includes: firstly, dividing the flash memory into a primary storage area and a backup storage area, wherein the difference between a first start address of the primary storage area and a second start address of the backup storage area is an offset address not equal to zero; reading the flash memory according to a address pointer equal to the first start address so as to obtain the boot data; making the electronic apparatus perform a boot sequence according to the boot data; then, detecting whether the boot sequence is normal or not, and when the boot sequence is abnormal, providing the flash memory with changing the read pointer to the second start address according to an offset address to read the backup boot data. | 09-27-2012 |
20150058544 | FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF - A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a command receiver, a command decoder and a core circuit. The command receiver sequentially receives a plurality of command data through the data input pin and the clock pin. The command decoder receives a command sequence formed by the command data, and compares the command sequence with a reference sequence to generate a reset signal. The core circuit receives the reset signal to activate a reset operation according to the reset signal. | 02-26-2015 |
Patent application number | Description | Published |
20110016263 | METHOD FOR PERFORMING DATA PATTERN MANAGEMENT REGARDING DATA ACCESSED BY A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management. | 01-20-2011 |
20110107141 | DATA STORAGE DEVICE, CONTROLLER, AND DATA ACCESS METHOD FOR A DOWNGRADE MEMORY - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses. | 05-05-2011 |
Patent application number | Description | Published |
20090213952 | METHOD FOR DEINTERLEAVING OFDM SIGNALS AND APPARATUS USING THE SAME - An apparatus for deinterleaving OFDM signals comprises a block deinterleaving memory, a computing module, a processed-tone buffer and a subcarrier rotator. The block deinterleaving memory is configured to store unprocessed symbols of the OFDM signals. The computing module is configured to access the block deinterleaving memory in accordance with the order of a first interleaving action for the OFDM signals and to compute thereafter. The processed-tone buffer is configured to store processed symbols of the OFDM signals. The subcarrier rotator is configured to access the processed-tone buffer and to perform a second interleaving action for the OFDM signals. | 08-27-2009 |
20100027612 | TRANSVERSAL FILTER - A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units. | 02-04-2010 |
20100253409 | CLOCK GENERATION SYSTEM AND CLOCK DIVIDING MODULE - A clock gating system includes a clock divider, a first clock gating unit and a second clock gating unit. The clock divider is employed to generate clock signals with different frequencies. The first clock gating unit is configured for generating a gated clock to a first functional block, while the second clock gating unit is configured for generating a gated clock to a second functional block. Logically the first clock gating unit and the second clock gating unit are included in the first functional block and the to second functional block, respectively, and in physical layout the first clock gating unit and the second clock gating unit are disposed close to the clock divider. | 10-07-2010 |
Patent application number | Description | Published |
20110080379 | DRIVING CIRCUIT - The present invention provides a driving circuit comprising a first data logic unit, a latch unit, and a determining unit. The first data logic unit is utilized for receiving at least a digital data signal and a first control signal, and for selectively inversing the digital data signal to generate a first digital output data signal according to the first control signal. The latch unit is utilized for receiving the first digital output data signal and a second control signal, and for selectively setting a second digital output data signal whether inversed from the first digital output data signal according to the second control signal. The determining unit is utilized for receiving the digital data signal and determining a transition number of the digital data signal in comparison with a previous digital data signal, and outputting the first control signal and the second control signal according to the transition number. | 04-07-2011 |
20120044021 | DIFFERENTIAL AMPLIFIER CIRCUIT - A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively. | 02-23-2012 |
20150341022 | HIGH-VOLTAGE LEVEL CONVERSION CIRCUIT - The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area. | 11-26-2015 |
Patent application number | Description | Published |
20090079627 | High Sensitivity GPS Receiver - A high sensitivity GPS receiver includes an acquisition engine and a tracking engine. The acquisition engine processes GPS satellite data at data rate that is substantially equal to twice the coarse acquisition (CA) code chip rate. This data rate advantageously enables the acquisition engine to process GPS satellite data with relatively less hardware area than traditional GPS acquisition approaches. In one embodiment, the high efficiency acquisition engine may be over-clocked, thereby allowing different phases of a CA code to be correlated quickly. The tracking engine can advantageously processes GPS satellite data at a data rate that does not have an integer relationship to the CA code chip rate. | 03-26-2009 |
20090322599 | SATELLITE NAVIGATIO RECEIVER HAVING CONFIGURABLE ACQUISITION AND TRACKING ENGINES - A satellite navigation receiver having a flexible acquisition and tracking engine architecture. The flexible acquisition engine has a reconfigurable delay line that can be used either as a single entity or divided into different sections. Consequently, it can be configured to search different satellite vehicles, a single Doppler frequency, and full CA code in parallel. When configuring the delay line into different sections, each section is used to search a partial CA code. In this configuration, multiple Doppler mode, multiple satellite vehicles, multiple Doppler frequencies, and partial CA code can be searched in parallel. Furthermore, the different sections of the CA code can be time-multiplexed into a correlator, which can then be over clocked to achieve full CA code correlation. The flexible tracking engine includes a number of parallel tracking channels, whereby each individual channel has a number of taps or fingers, which can be used to lock onto different delays. During tracking, one of the taps can be used to lock on to the center of the peak. This leaves the other taps free to be used to perform other functions, such as determining the shape of the peak, detecting earlier arrivals for line of sight component, and obtaining an estimate of the noise floor. The flexible tracking engine is configurable to help acquisition functions, such as fine acquisition, false trigger detection, and/or fast reacquisition. | 12-31-2009 |
20110090112 | SATELLITE NAVIGATION RECEIVER HAVING A CONFIGURABLE ACQUISITION ENGINE - A satellite navigation receiver having a flexible acquisition and tracking engine architecture. The flexible acquisition engine has a reconfigurable delay line that can be used either as a single entity or divided into different sections. Consequently, it can be configured to search different satellite vehicles, a single Doppler frequency, and full CA code in parallel. When configuring the delay line into different sections, each section is used to search a partial CA code. In this configuration, multiple Doppler mode, multiple satellite vehicles, multiple Doppler frequencies, and partial CA code can be searched in parallel. Furthermore, the different sections of the CA code can be time-multiplexed into a correlator, which can then be over clocked to achieve full CA code correlation. The flexible tracking engine includes a number of parallel tracking channels, whereby each individual channel has a number of taps or fingers, which can be used to lock onto different delays. During tracking, one of the taps can be used to lock on to the center of the peak. This leaves the other taps free to be used to perform other functions, such as determining the shape of the peak, detecting earlier arrivals for line of sight component, and obtaining an estimate of the noise floor. The flexible tracking engine is configurable to help acquisition functions, such as fine acquisition, false trigger detection, and/or fast reacquisition. | 04-21-2011 |
20110181468 | Digital Front End In System Simultaneously Receiving GPS And GLONASS Signals - A receiver for receiving both GPS signals and GLONASS signals is provided. This receiver includes an analog front end (AFE), a GPS digital front end (DFE) and a GLONASS DFE for receiving an output of the AFE, and a dual mode interface (DMI) for receiving outputs of the GPS and GLONASS DFEs. Search engines are provided for receiving outputs of the DMI. Notably, certain front-end components of the AFE are configured to process both the GPS signals and the GLONASS signals. | 07-28-2011 |
20120281734 | High Sensitivity GPS Receiver - A high sensitivity GPS receiver includes an acquisition engine and a tracking engine. The acquisition engine processes GPS satellite data at data rate that is substantially equal to twice the coarse acquisition (CA) code chip rate. This data rate advantageously enables the acquisition engine to process GPS satellite data with relatively less hardware area than traditional GPS acquisition approaches. In one embodiment, the high efficiency acquisition engine may be over-clocked, thereby allowing different phases of a CA code to be correlated quickly. The tracking engine can advantageously process GPS satellite data at a data rate that does not have an integer relationship to the CA code chip rate. | 11-08-2012 |
20140028499 | Engines In System Simultaneously Receiving GPS And GLONASS Signals - A receiver for receiving both GPS signals and GLONASS signals is provided. This receiver includes an analog front end (AFE), a GPS digital front end (DFE) and a GLONASS DFE for receiving an output of the AFE, and a dual mode interface (DMI) for receiving outputs of the GPS and GLONASS DFEs. Search engines are provided for receiving outputs of the DMI. Notably, certain front-end components of the AFE are configured to process both the GPS signals and the GLONASS signals. | 01-30-2014 |
Patent application number | Description | Published |
20130317935 | REVERSE AUCTION SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT - A reverse auction system of the present disclosure is provided and includes an account module, a server center, a searching module, a publishing module, and a bidding module. The account module registers or charges a desired article request from a buyer side. The server center converts the desired article request into publishing data and searching data. The searching module connects to at least one auction website for collaborating therewith to perform comparison in accordance with the searching data, and then returns a feedback signal of a comparison result. Furthermore, the publishing module publishes the publishing data, and then the bidding module offers a platform to the suppliers or bidders to bid for the buyer's desired article described in the publishing data. The work of the publishing module and the bidding module is in parallel with the work of the searching module. | 11-28-2013 |
20140149253 | TASKING SYSTEM FOR MANUFACTURING AN ELECTRONIC UNIT, TRADING SYSTEM FOR A CUSTOMIZED ELECTRONIC UNIT, QUALITY CONTROLLING SYSTEM FOR TRADING A CUSTOMIZED ELECTRONIC UNIT AND METHODS THEREOF - A tasking system for manufacturing an electronic unit is provided. The tasking system is connected to a network platform, the electronic unit includes at least a board circuit and an IC chip corresponded to an IC program. The tasking system includes a task assignment side, a first task processing side and a second task processing side. The task assignment side is connected to the network platform for proving a task requesting table and publishes the task requesting table to the network platform, wherein the task requesting table is corresponded to the electronic unit. The first task processing side is connected to the network platform. The first task processing side constructs the IC chip in accordance with the task requesting table. The second task processing side is connected to the network platform, and the second task processing side constructs the board circuit in accordance with the task requesting table. | 05-29-2014 |