Patent application number | Description | Published |
20120013825 | LIQUID CRYSTAL DISPLAY DEVICE WITH SWITCHABLE VIEWING ANGLE - A viewing angle switchable liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a plurality of color sub-pixels and a plurality of viewing angle control (VAC) pixels. The liquid crystal layer includes liquid crystal molecules sandwiched between the first substrate and the second substrate. The liquid crystal molecules of each color sub-pixel include twisted nematic liquid crystal molecules. Each of the color sub-pixels includes a first pixel electrode disposed on an inner surface of the first substrate, and a second pixel electrode disposed on an inner surface of the second substrate. Each of the viewing angle control pixels includes a first electrode and a second electrode disposed on the inner surface of the first substrate, and a third electrode disposed on the inner surface of the second substrate. | 01-19-2012 |
20120075562 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first regions and a plurality of second regions. The first regions and the second regions are formed on the first substrate and the second substrate. In a narrow viewing mode, the luminous flux of the first regions along a first viewing direction is different from that of the first regions along a second viewing direction opposite to the first viewing direction, and the luminous flux of the second regions along the first viewing direction is substantially different from that of the first regions along the first viewing direction. | 03-29-2012 |
20130100112 | IMAGE PRIVACY PROTECTING METHOD - An image privacy protecting method is provided. Positions of a privacy protecting region and a normal display region are acknowledged first. When a frame of image is processed, a first image data will be displayed in the privacy protecting region is processed in a narrow viewing mode to obtain a narrow viewing driving data, and a second image data will be displayed in the normal display region is processed in a wide viewing mode to obtain a wide viewing driving data. Finally, display operations are performed in the privacy protecting region and the normal display region respectively according to the narrow viewing driving data and the wide viewing driving data. | 04-25-2013 |
20130100182 | COMPENSATION METHOD FOR PRIVACY-IMAGE PROTECTION - A compensation method for privacy-image protection is provided. The compensation method operates a display device in a narrow visual-angle mode, then determines where is data to be displayed according to a relative position between the data to be displayed and a specific object, and finally determines to use which to adjust the data to be displayed according to the determined result, and displays the data. | 04-25-2013 |
20140063386 | PEEP-PROOF DISPLAY APPARATUS AND DRIVING METHOD THEREOF - A peep-proof display apparatus includes a plurality of sub-pixels disposed between a first substrate and a second substrate. Each sub-pixel includes a first conductive layer, a color filter layer, an isolation film, a light modulator layer, a second conductive layer, an insulation film and a third conductive layer. The color filter layer is disposed between the first conductive layer and the isolation film. The light modulator layer is disposed between the isolation film and the second conductive layer. The insulation film is disposed between the second and third conductive layers. In a first display mode, the light modulator layer is applied with an electric field parallel thereto. In a second display mode, the light modulator layer is applied with an electric field parallel thereto and an electric field perpendicular thereto. | 03-06-2014 |
20140191933 | ADJUSTABLE VIEWING ANGLE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME - Disclosed herein is an adjustable viewing angle display device. The display device includes a display panel composed of a first substrate, a second substrate, a display medium layer interposed therebetween, a first electrode, a second electrode and a third electrode. Pluralities of sub-pixels are defined in the display panel. The first and second electrodes are disposed on the first substrate in the sub-pixels. The first electrode is spaced apart from the second electrode. The third electrode is disposed on the second substrate. When the display device is operated in a narrow viewing angle mode, there exists a non-zero potential difference between the second electrode and the third electrode, and when the sub-pixel is at gray level of zero, the potential difference between the first electrode and the second electrode is not zero. A driving method for driving the display device is disclosed as well. | 07-10-2014 |
20140192091 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - Disclosed herein is a display device with an adjustable viewing angle. The display device at least includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel. When the display device is operated in a wide viewing angle mode, the first and second sub-pixels each have an on-axis brightness at a predetermined gray level. When the display device is operated in a narrow viewing angle mode, the first and second sub-pixels respectively have a first on-axis brightness at a first gray level and a second on-axis brightness at a second gray level. The first on-axis brightness at the first gray level is substantially less than the on-axis brightness at the predetermined gray level of the first sub-pixel. | 07-10-2014 |
20150049288 | PIXEL STRUCTURE - A pixel structure includes a patterned insulating layer and a patterned electrode layer. The patterned insulating layer includes a first area and a second area, and the patterned electrode layer includes a third layer and a fourth layer. The first area has a plurality of bar-shaped structures, the third area is a block electrode, and the fourth area is composed of a plurality of first bar-shaped electrodes. The third area is disposed opposite to the first area such that the third area is protruded according to the bar-shaped structures thereby forming a plurality of second bar-shaped electrodes. The fourth area is disposed opposite to the second area such that the first bar-shaped electrodes are formed on the second area. | 02-19-2015 |
Patent application number | Description | Published |
20110177668 | METHOD OF MAKING A THIN FILM RESISTOR - A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole. | 07-21-2011 |
20110193174 | Multiple Silicide Integration Structure and Method - A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices. | 08-11-2011 |
20110318898 | HARD MASK FOR THIN FILM RESISTOR MANUFACTURE - Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer. | 12-29-2011 |
20120018811 | FORMING BIPOLAR TRANSISTOR THROUGH FAST EPI-GROWTH ON POLYSILICON - Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well. | 01-26-2012 |
20120086099 | SCHOTTKY DIODE - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region. | 04-12-2012 |
20120267753 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area. | 10-25-2012 |
20130034816 | Conductive Vias In A Substrate - A method of forming a conductive via in a substrate includes forming a via hole covered by a dielectric layer followed by an annealing process. The dielectric layer can getter the mobile ions from the substrate. After removing the dielectric layer, a conductive material is formed in the via hole, forming a conductive via in the substrate. | 02-07-2013 |
20130043541 | LOW POWER/HIGH SPEED TSV INTERFACE DESIGN - A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage. | 02-21-2013 |
20130082364 | EMI Package AND METHOD FOR MAKING SAME - An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer. | 04-04-2013 |
20130147057 | THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT - Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in | 06-13-2013 |
20130168805 | Packages with Passive Devices and Methods of Forming the Same - A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM. | 07-04-2013 |
20130264684 | Methods and Apparatus of Wafer Level Package for Heterogeneous Integration Technology - Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections. | 10-10-2013 |
20130285200 | Capacitor for Interposers and Methods of Manufacture Thereof - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate. | 10-31-2013 |
20130320553 | NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION - An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters. | 12-05-2013 |
20140001635 | Package with Passive Devices and Method of Forming the Same | 01-02-2014 |
20140029205 | Band Pass Filter for 2.5D/3D Integrated Circuit Applications - The present disclosure relates to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip comprising a plurality of capacitors embedded in a common molding compound along with a transceiver chip, and arranged within a polymer package. Ultra-thick metallization layers are disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layers also form a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area penalty as compared to conventional solutions. The band pass filter may also be coupled to a plurality of solder balls comprising a Flip Chip Ball Grid Array suitable for 2.5D and 3D integrated circuit applications. | 01-30-2014 |
20140042612 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure. | 02-13-2014 |
20140042643 | Interposer System and Method - A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region. | 02-13-2014 |
20140073091 | Packages with Passive Devices and Methods of Forming the Same - A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM. | 03-13-2014 |
20140203429 | FAN-OUT PACKAGE STRUCTURE AND METHODS FOR FORMING THE SAME - A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. A polymer region includes first portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first plurality of metal pillars and top ends of the second plurality of metal pillars. Redistribution lines are formed over and electrically coupled to the first and the second plurality of metal pillars. | 07-24-2014 |
20140252572 | Structure and Method for 3D IC Package - Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive elements, and encapsulating in a second molding compound the second dies and the underfill. The chip package comprises a chip encapsulated in a molding compound, and a larger chip coupled to the first chip via conductive elements, wherein the conductive elements are encapsulated in an underfill between the chip and the larger chip without an interposer, and wherein the larger chip and the underfill are encapsulated in a second molding compound in contact with the molding compound. | 09-11-2014 |
20140252646 | Interconnect Structure for Package-on-Package Devices - An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package. | 09-11-2014 |
20140264933 | Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method - Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound. | 09-18-2014 |
20140295624 | Package with Passive Devices and Method of Forming the Same - An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar. | 10-02-2014 |
20140319696 | 3D Packages and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a method including placing a plurality of dies over a passivation layer, the plurality of dies comprising at least one active device, molding the plurality of dies with a first molding material, and forming a plurality of through-package vias (TPVs) in the first molding material, first surfaces of the plurality of TPVs being substantially coplanar with a backside surfaces of the plurality of dies. The method further includes patterning the passivation layer to expose a portion of the first surfaces of the plurality of TPVs, and bonding a plurality of top packages to the first surfaces of the plurality of TPVs. | 10-30-2014 |
20140346671 | Fan-Out Package Structure and Methods for Forming the Same - A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. One of the device die and the plurality of dies includes a semiconductor substrate and a through-via penetrating through the semiconductor substrate, A polymer region includes portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first and the second plurality of metal pillars. Redistribution lines are formed over the first and the second plurality of metal pillars. | 11-27-2014 |
20140367160 | ELECTRIC MAGNETIC SHIELDING STRUCTURE IN PACKAGES - A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line. | 12-18-2014 |
20150024547 | EMI Package and Method for Making Same - An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer. | 01-22-2015 |
20150048500 | Multi-Chip Structure and Method of Forming Same - A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer. The device further comprises a redistribution layer formed on a top surface of a first side of the encapsulation layer, wherein the redistribution layer is connected to active circuits of the first chip and the second chip and the redistribution layer extends beyond at least one edge of the first chip and the second chip. | 02-19-2015 |
20150084190 | Multi-Chip Package Structure and Method of Forming Same - A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures. | 03-26-2015 |
20150084191 | Multi-Chip Package and Method of Formation - A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures. | 03-26-2015 |
20150115464 | Chip on Package Structure and Method - A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die. | 04-30-2015 |
20150115470 | Chip on Package Structure and Method - A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die. Alternatively, instead of forming vias over the carrier wafer, through silicon vias may be formed within a semiconductor substrate and the semiconductor substrate may be attached to the carrier wafer. | 04-30-2015 |
Patent application number | Description | Published |
20090108290 | Source/Drain Strained Layers - A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer. | 04-30-2009 |
20100289086 | Source/Drain Strained Layers - A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer. | 11-18-2010 |
20110230022 | Source/Drain Strained Layers - A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer. | 09-22-2011 |
20140147943 | Method for Determining Carrier Concentrations in Semiconductor Fins - A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance. | 05-29-2014 |
20140256105 | Self-Aligned Passivation of Active Regions - A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET). | 09-11-2014 |
20150041918 | Self-Aligned Dual-Metal Silicide and Germanide Formation - A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals. | 02-12-2015 |
20150062561 | Stress Analysis of 3-D Structures Using Tip-Enhanced Raman Scattering Technology - A method includes performing a first probing on a sample integrated circuit structure to generate a first Raman spectrum. During the first probing, a first laser beam having a first wavelength is projected on the sample integrated circuit structure. The method further includes performing a second probing on the sample integrated circuit structure to generate a second Raman spectrum, wherein a Tip-Enhanced Raman Scattering (TERS) method is used to probe the sample integrated circuit structure. During the second probing, a second laser beam having a second wavelength different from the first wavelength is projected on the sample integrated circuit structure. A stress in a first probed region of the sample integrated circuit structure is then from the first Raman spectrum and the second Raman spectrum. | 03-05-2015 |
20150076499 | System and Method for Test Key Characterizing Wafer Processing State - Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group. | 03-19-2015 |
20150097239 | Passivation Structure of Fin Field Effect Transistor - A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material. | 04-09-2015 |
Patent application number | Description | Published |
20120015459 | Thermal Leveling for Semiconductor Devices - A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution. | 01-19-2012 |
20130089958 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 04-11-2013 |
20140024187 | FINLIKE STRUCTURES AND METHODS OF MAKING SAME - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 01-23-2014 |
20140302653 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 10-09-2014 |
20150024566 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 01-22-2015 |
20150024588 | Hard Mask Removal Scheme - A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is located through the dielectric layer and the hard mask layer. A filler layer is formed in the via hole and over the barrier layer. The filler layer and the hard mask layer are removed. A metal layer is formed in the via hole. | 01-22-2015 |
20150107634 | Apparatus and Methods for Movable Megasonic Wafer Probe - A movable wafer probe may include: an immersion hood including a top body portion and a bottom foot portion, the top body portion having first inner sidewalls surrounding a top opening, the bottom foot portion having second inner sidewalls surrounding a bottom opening; a transducer disposed above the bottom opening and within the top opening, the transducer spaced apart from the first inner sidewalls of the top body portion by a first spacing, the first spacing forming a fluid exhaust port; and a fluid input port extending through the transducer, a bottom end of the fluid input port opening to the bottom opening | 04-23-2015 |
Patent application number | Description | Published |
20110265051 | Method for Substrate Noise Analysis - In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal. | 10-27-2011 |
20120119845 | Balun System and Method - A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers. | 05-17-2012 |
20120133471 | High-k Transformers Extending into Multiple Dielectric Layers - A device includes a first plurality of dielectric layers over a substrate and a second plurality of dielectric layers over the first plurality of dielectric layers. A metal inductor includes a first metal portion, a second metal portion, a third metal portion, and a fourth metal portion, wherein each of the first, the second, the third, and the fourth metal portions extends into the first and the second plurality of dielectric layers. A first metal bridge connects the first metal portion to the second metal portion, wherein the first metal bridge extends into the first plurality of dielectric layers and not into the second plurality of dielectric layers. A second metal bridge connects the third metal portion to the fourth metal portion, wherein the second metal bridge extends into the second plurality of dielectric layers and not into the first plurality of dielectric layers. | 05-31-2012 |
20120147578 | Radio-Frequency Packaging with Reduced RF Loss - A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices. | 06-14-2012 |
20120286836 | Built-in Self-test Circuit for Voltage Controlled Oscillators - A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal. | 11-15-2012 |
20120286888 | Switched Capacitor Array for Voltage Controlled Oscillator - A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code. | 11-15-2012 |
20130154011 | Methods and Apparatus for Reduced Gate Resistance FinFET - Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed. | 06-20-2013 |
20130288443 | Methods for Reduced Gate Resistance FINFET - Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed. | 10-31-2013 |
20140264635 | RF Switch on High Resistive Substrate - A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. | 09-18-2014 |
Patent application number | Description | Published |
20100007390 | Clock generating circuit, power converting system, and related method with spread spectrum for EMI reduction - A clock signal generating circuit includes a main delay circuit and a variable delay circuit. The main delay circuit receives a feedback clock signal, and outputs an output clock signal after a first delay when receiving the feedback clock signal. The variable delay circuit receives the output clock signal, and updates the feedback clock signal after a second delay when receiving the output clock signal. The second delay is periodically varied and is shorter than the first delay. | 01-14-2010 |
20100124080 | CURRENT CONTROL METHOD AND APPARATUS - Current control method and apparatus are disclosed. A current limiter is coupled to a switch connected in series with an energy transfer element of a power supply. The current limiter detects a current flowing through the switch and, when the current exceeds a current limit signal, turns off the switch. A limit signal generator provides the current limit signal, detects the maximum current value of the current, and updates the current limit signal according to the maximum current value and an ideal current limit value. | 05-20-2010 |
20100237960 | FREQUENCY-JITTERING APPARATUSES, FREQUENCY-JITTERING METHODS AND POWER MANAGEMENT DEVICES - A frequency-jittering apparatuses includes an oscillator and a frequency control circuit. The oscillator generates a signal. When the magnitude of the signal exceeds a magnitude of a reference signal, the oscillator operates substantially in a first state; and when the magnitude of the signal is lower than the magnitude of the reference signal, the oscillator operates substantially in a second state different from the first one. The frequency control circuit varies the reference signal to change the frequency of the signal output from the oscillator. | 09-23-2010 |
20100321956 | CONTROL METHOD, CONSTANT CURRENT CONTROL METHOD, METHOD FOR GENERATING A REAL CURRENT SOURCE TO REPRESENT AVERAGE CURRENT THROUGH A WINDING, CONSTANT CURRENT AND CONSTANT VOLTAGE POWER CONVERTER, SWITCH CONTROLLER, AND AVERAGE VOLTAGE DETECTOR - An embodiment provides a control method capable of controlling a switching-mode power supply to provide an output power source. The switching-mode power supply has a winding coupled to an input power source and controlled by a switch to be energized or de-energized. The maximum current peak through the winding is set to be a predetermined value. A discharge time of the winding in a switching cycle period is detected. The switching cycle period of the switch is controlled to keep the ratio of the discharge time to the switching cycle period as a constant. | 12-23-2010 |
20110032730 | SAMPLING CIRCUIT AND CONTROL METHOD - An embodiment provides a sampling circuit, which has a sampling capacitor and a voltage compensation circuit. The voltage compensation circuit has a reference capacitor and a compensation circuit. The sampling capacitor samples a voltage signal and memorizes the signal as a sampling signal. The reference capacitor memorizes a reference signal with a predetermined value. The compensation circuit changes the reference signal with a recovery amount to recover the reference signal to the predetermined value, and simultaneously changes the sampling signal with an adjustment amount. | 02-10-2011 |
20110141778 | SWITCH CONTROLLER FOR SWITCHING POWER SUPPLY AND METHOD THEREOF - A switch controller for switching power supply is coupled to an auxiliary winding of the switching power supply through a detecting resistor. The switch controller provides a detecting current passing through the detecting resistor for keeping the voltage level of a detecting signal transmitted by the detecting resistor higher than a predetermined voltage. In this way, the switch controller can avoid the latch-up phenomenon caused by receiving the detecting signal of the negative voltage level. In addition, the switch controller can detect the magnitude of an input voltage of the switching power supply by means of the detecting current, and accordingly control the operation of the switching power supply. | 06-16-2011 |
20110149612 | Control Method and Controller with constant output current control - Control method and related controller, applicable to a power supply with a switch and an inductive device. The inductive current through the inductive device is sensed. An operating frequency of the switch is controlled to make an average of the inductive current substantially equal to a predetermined portion of the peak of the inductive current and to make the inductive device operated in continuous conduction mode. | 06-23-2011 |
20110156680 | Methods and related controllers for controlling output power of a power supply - A method of controlling a power supply comprising a switch and an inductive device includes turning the switch on to energize the inductive device, detecting inductor current flowing through the inductive device to generate a current sensing signal, comparing a peak of the current sensing signal and a limiting signal to generate an adjustment value, and comparing the current sensing signal and the limiting signal. The switch is closed when the current sensing signal, the limiting signal, and the adjustment value are approximately in a specific relationship for approximately equalizing a next peak of the current sensing signal to the limiting signal to cancel signal delay influence. | 06-30-2011 |
20110211372 | COMPENSATION CIRCUITS AND CONTROL METHODS OF SWITCHED MODE POWER SUPPLY - A compensation circuit has a resistor, a switch and a compensation capacitor. The resistor and the switch are connected in series between a power node and a compensation node. The compensation capacitor is connected to the compensation node, whose voltage is responsive to the output power source. For a predetermined period of time after the voltage falls below a predetermined value, the switch is open and no current flows through the resistor from the power node to the compensation node. | 09-01-2011 |
20120008343 | High-Voltage Startup Method and Power Management Apparatus - A high-voltage device provides a constant current drained from a high voltage source to charge a filter capacitor, where a voltage level of the higher voltage source is higher than 90 volts. When the operation voltage of the filter capacitor exceeds a first predetermined value, the charging of the filter capacitor by the constant current is stopped. A feedback loop is then used to maintain the operating voltage at substantially a second predetermined value lower than the first one. | 01-12-2012 |
20120019329 | Frequency-jittering apparatuses, frequency-jittering methods and power management devices - A frequency-jittering apparatuses includes an oscillator and a frequency control circuit. The oscillator generates a signal. When the magnitude of the signal exceeds a magnitude of a reference signal, the oscillator operates substantially in a first state; and when the magnitude of the signal is lower than the magnitude of the reference signal, the oscillator operates substantially in a second state different from the first one. The frequency control circuit varies the reference signal to change the frequency of the signal output from the oscillator. | 01-26-2012 |
20120161727 | Power Control Circuits and Methods - In a switching mode power supply, a power controlling circuit includes a phase generator and a phase controller. The phase generator provides a clock signal. The phase controller detects phases of a phase reference signal and a burst initialization signal so as to generate a burst signal, and causes a phase of the burst signal to not be earlier than the phase of the group reference signal. The burst signal is utilized for switching the power supply between a non-switching state and a switching state. The group reference signal is generated according to the clock signal and has a lower frequency than the clock signal. The burst initialization signal is controlled by an output voltage source of the power supply. | 06-28-2012 |
20130070486 | CONTROL METHODS AND CONTROLLERS - Control methods and controller thereof for a power supply including a power switch and an inductor. The power switch is turned on to increase the inductor current through the inductor, which is sensed to generate a current-sense signal. The current-sense signal is added up with an adjusting signal to generate a summation signal. The power switch is turned off if the summation signal is higher than a peak limit. The turn-on time of the power switch is detected to update the adjusting signal. | 03-21-2013 |
20130135905 | CONTROL METHODS FOR SWITCHING POWER SUPPLIES - An embodiment provides a control method capable of controlling a switching-mode power supply to provide an output power source. The switching-mode power supply has a winding coupled to an input power source and controlled by a switch to be energized or de-energized. The maximum current peak through the winding is set to be a predetermined value. A discharge time of the winding in a switching cycle period is detected. The switching cycle period of the switch is controlled to keep the ratio of the discharge time to the switching cycle period as a constant. | 05-30-2013 |