Patent application number | Description | Published |
20080251824 | Semiconductor memory device and manufacturing method thereof - A semiconductor memory device and a manufacturing method thereof are provided which enable cell-contact plugs to be formed at high yields and the yields of semiconductor memory devices to be improved in the manufacturing process. The semiconductor memory device includes: a semiconductor substrate; MOS transistors which are formed on a surface of the semiconductor substrate; a cell-contact plug which is made of poly-silicon film, is located between gates of the MOS transistors, and is connected to a source or a drain of one of the MOS transistors; a pad metal layer which is formed on the cell-contact plug; an interlayer dielectric film which is formed on the pad metal layer; a storage capacitor which is formed on the interlayer dielectric film; and a contact plug which is formed inside an opening which penetrates the interlayer dielectric film, and connects the storage capacitor with the pad metal layer. | 10-16-2008 |
20090061592 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing the semiconductor device includes forming a first polysilicon film on an active region and an element isolation region made of a dielectric material provided in a semiconductor substrate; forming a hard mask on the first polysilicon film; etching the first polysilicon film, the semiconductor substrate in the active region and the dielectric material in the element isolation region by using the hard mask to form first and second gate trenches in the active region and the element isolation region, respectively; and filling the first and second gate trenches with a second polysilicon film before the hard mask is removed. | 03-05-2009 |
20090085108 | SEMICONDUCTOR DEVICE HAVING CELL TRANSISTOR WITH RECESS CHANNEL STRUCTURE - The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an N-type polysilicon layer which contains of N-type impurities at an approximately constant concentration. | 04-02-2009 |
20090148994 | Method of manufacturing semiconductor device with recess gate transistor - A method of manufacturing a semiconductor device includes forming a plurality of recesses in a semiconductor substrate, forming a gate insulating film in the plurality of recesses, and a plurality of gate electrodes on the gate insulating film in the plurality of recesses, forming an insulating layer on the semiconductor substrate and the plurality of gate electrodes, forming a plurality of contact holes in the insulating layer, the contact holes being formed between adjacent ones of the plurality of gate electrodes, implanting a first impurity into the semiconductor substrate through the plurality of contact holes to form each of source and drain regions in contact with the gate insulating film. | 06-11-2009 |
20100127317 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a memory cell array region including a plurality of memory cells, an annular groove surrounding the memory cell array region, a protective insulating film covering the inner wall of the annular groove, and a conductor filling the annular groove. | 05-27-2010 |
20110081761 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding portion of the semiconductor substrate surrounded by the first recess. The protruding portion has a sloped side surface. A first insulating film that fills the first recess is formed. A gate recess is formed in the active region to form a thin film portion that upwardly extends. The thin film portion is positioned between the gate recess and the first insulating film. The thin film portion is a part of the protruding portion. An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion. | 04-07-2011 |
20110266603 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode. | 11-03-2011 |
20150145011 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode. | 05-28-2015 |