Patent application number | Description | Published |
20080266966 | OPERATION METHOD OF NON-VOLATILE MEMORY AND METHOD OF IMPROVING COUPLING INTERFERENCE FROM NITRIDE-BASED MEMORY - An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window. | 10-30-2008 |
20090180332 | OPERATION METHOD OF NITRIDE-BASED FLASH MEMORY AND METHOD OF REDUCING COUPLING INTERFERENCE - A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window. | 07-16-2009 |
20100112797 | METHOD FOR FORMING A MEMORY ARRAY - The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed. | 05-06-2010 |
20100284220 | OPERATION METHOD OF NON-VOLATILE MEMORY - An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels. | 11-11-2010 |
20100289093 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface. | 11-18-2010 |
20100302845 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits. | 12-02-2010 |
20100302855 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively. | 12-02-2010 |
20100314680 | MEMORY ARRAY - A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall. | 12-16-2010 |
20110080784 | NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF - An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1 | 04-07-2011 |
20110122690 | METHOD FOR PROGRAMMING MULTI-LEVEL CELL AND MEMORY APPARATUS - A method for programming a multi-level cell and a memory apparatus are described, wherein each cell has two storage sites. The method includes making the first storage site have a first Vt level and the second storage site have a second Vt level. The first Vt level is selected from M Vt levels. When the first Vt level is the i-th level among the M Vt levels, the second Vt level is selected from n | 05-26-2011 |
20110182123 | FLASH MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF - A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion. | 07-28-2011 |
20110189836 | ION/IOFF IN SEMICONDUCTOR DEVICES BY UTILIZING THE BODY EFFECT - A method for reducing leakage current of a semiconductor device includes supplying a substantially constant and non-zero bulk bias to a relatively low threshold voltage semiconductor device during formation of a conductive channel of the semiconductor device and during the formation of a non-conductive channel of the semiconductor device. | 08-04-2011 |
20120008388 | NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF - An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group and the secondary voltage distribution groups includes N threshold-voltage distribution curves, and N is an integer greater than 2; selecting a first operation level and a second operation level according to a programming command; programming the first storage position according to the threshold-voltage distribution curve corresponding to the first operation level in the main voltage distribution group; selecting one of the secondary voltage distribution groups according to the first operation level and programming the second storage position according to the threshold-voltage distribution curve corresponding to the second operation level in the selected secondary voltage distribution group. | 01-12-2012 |
20120056259 | MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL - A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region. | 03-08-2012 |
20120126307 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. | 05-24-2012 |
20120127795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF AND OPERATING METHOD OF MEMORY CELL - A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell. | 05-24-2012 |
20120140556 | METHOD OF OPERATING FLASH MEMORY - A method of operating a flash memory is described. When a first storage site has 2 | 06-07-2012 |
20120243334 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the i | 09-27-2012 |
20120261739 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate, and a dielectric layer is provided. The first doped region is located in a substrate and has a trench. The second doped region is located at the bottom of the trench to separate the first doped region into a source doped region and a drain doped region. A channel region is located between the source doped region and the drain doped region. The gate is located in the trench. The dielectric layer covers the sidewall and the bottom of the trench and separates the gate and the substrate. | 10-18-2012 |
20120287539 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 1 | 11-15-2012 |
20130155554 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a clamp unit and a control circuit. The clamp unit provides a discharging path from a first power line to a first ground line. The control circuit receives a first power voltage from the first power line and a second power voltage from a second power line. Wherein, when the first power voltage and the second power voltage are applied, the control circuit generates an isolation signal to disconnect the discharging path. When the first power voltage and the second power voltage are not applied, the control circuit generates a trigger signal according to an electrostatic signal from the first power line to turn on the discharging path. | 06-20-2013 |
20140092504 | Electrostatic discharge protection device - An electrostatic discharge protection device including a silicon-controlled rectifier and a path switching circuit is provided. The silicon-controlled rectifier includes a first connection terminal, a second connection terminal, a first control terminal and a second control terminal, wherein the first connection terminal and the second connection terminal are respectively connected to a first line and a second line. The path switching circuit is electrically connected to the first line, the first control terminal and the second control terminal. When an input signal is supplied to the first line, the path switching circuit provides a first current path from the first line to the first control terminal in response to the input signal. When an electrostatic pulse is appeared on the first line, the path switching circuit provides a second current path from the first control terminal to the second control terminal in response to the electrostatic pulse. | 04-03-2014 |
20140126296 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A j | 05-08-2014 |
20140159134 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure. | 06-12-2014 |
20140231900 | NON-VOLATILE MEMORY - A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface. | 08-21-2014 |
20150023098 | OPERATION METHOD OF MULTI-LEVEL MEMORY - An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level. | 01-22-2015 |