Patent application number | Description | Published |
20140281283 | DUAL HOST EMBEDDED SHARED DEVICE CONTROLLER - Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data. | 09-18-2014 |
20150032908 | USING USB SIGNALING TO TRIGGER A DEVICE TO ENTER A MODE OF OPERATION - A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation. | 01-29-2015 |
20150032909 | USING USB SIGNALING TO TRIGGER A DEVICE TO ENTER A MODE OF OPERATION - A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation. | 01-29-2015 |
20150046732 | SYSTEM AND METHOD FOR MEMORY CHANNEL INTERLEAVING WITH SELECTIVE POWER OR PERFORMANCE OPTIMIZATION - Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance. | 02-12-2015 |
20150242213 | SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY - Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM. | 08-27-2015 |
20150243373 | KERNEL MASKING OF DRAM DEFECTS - Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold. | 08-27-2015 |
20150261632 | SYSTEMS AND METHODS FOR REDUCING MEMORY FAILURES - Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation. | 09-17-2015 |
20150293822 | SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS - Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation. | 10-15-2015 |
20160054928 | SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP - Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space. | 02-25-2016 |
20160077959 | System and Method for Sharing a Solid-State Non-Volatile Memory Resource - A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators. | 03-17-2016 |