Patent application number | Description | Published |
20100057740 | ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY - A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions. | 03-04-2010 |
20100058344 | ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY - A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions. | 03-04-2010 |
20100153953 | UNIFIED OPTIMISTIC AND PESSIMISTIC CONCURRENCY CONTROL FOR A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM - A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled. | 06-17-2010 |
20110145512 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 06-16-2011 |
20120159495 | NON-BLOCKING WAIT-FREE DATA-PARALLEL SCHEDULER - Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed. | 06-21-2012 |
20120254497 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 10-04-2012 |
20120272210 | METHODS AND SYSTEMS FOR MAPPING A FUNCTION POINTER TO THE DEVICE CODE - Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device. | 10-25-2012 |
20130046924 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 02-21-2013 |
20130046925 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 02-21-2013 |
20130046947 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 02-21-2013 |
20140071144 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 03-13-2014 |
20140156953 | Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System - A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled. | 06-05-2014 |