Yang, Mountain View

Barbara Jer-Chee Yang, Mountain View, CA US

Patent application number	Description	Published
20090173784	METHOD AND SYSTEM FOR PERFORMING A CARD-PRESENT TRANSACTION USING IMAGE CAPTURE ON A PORTABLE DEVICE - Some embodiments of the present invention provide a system that processes a financial transaction involving a portable device and a transaction server. During operation, the system obtains transaction data associated with the financial transaction that includes a transaction amount, credit card information, and an image of a credit card. The system then sends the transaction data to the transaction server using the portable device. Next, the system verifies a card-present transaction using the transaction data and determines a validity of the transaction data. If the transaction data is valid, the transaction server processes the financial transaction and sends an authorization code confirming the financial transaction to the portable device.	07-09-2009

Beverly Yang, Mountain View, CA US

Patent application number	Description	Published
20110208756	ONLINE RANKING METRIC - Methods, systems, and apparatus, including computer program products, for ranking resources. One or more signals reporting one or more actions by the plurality of users related to a respective resource are received, where a reported action is a presentation of the respective resource, an addition of the respective resource, or a deletion of the respective resource. The reported actions include one or more short deletions of the respective resource. A respective long-addition click-through rate (LACTR) is determined for the respective resource based on a number of reported presentations of the respective resource and a difference between a number of reported additions of the respective resource and a number of short deletions of the respective resource. The plurality of resources are ranked based on the respective LACTRs for the plurality of resources. The ranking of the plurality of resources are provided.	08-25-2011
20110270916	GENERIC ONLINE RANKING SYSTEM AND METHOD SUITABLE FOR SYNDICATION - Methods, systems, and apparatus, including computer program products, for ranking resources. One or more signals reporting one or more actions by the plurality of users related to a respective resource are received, where a reported action is a presentation of the respective resource, an addition of the respective resource, or a deletion of the respective resource. The reported actions include one or more short deletions of the respective resource. A respective long-addition click-through rate (LACTR) is determined for the respective resource based on a number of reported presentations of the respective resource and a difference between a number of reported additions of the respective resource and a number of short deletions of the respective resource. The plurality of resources are ranked based on the respective LACTRs for the plurality of resources. The ranking of the plurality of resources are provided.	11-03-2011
20120254198	Online Ranking Metric - Methods, systems, and apparatus, including computer program products, for ranking resources. One or more signals reporting one or more actions by the plurality of users related to a respective resource are received, where a reported action is a presentation of the respective resource, an addition of the respective resource, or a deletion of the respective resource. The reported actions include one or more short deletions of the respective resource. A respective long-addition click-through rate (LACTR) is determined for the respective resource based on a number of reported presentations of the respective resource and a difference between a number of reported additions of the respective resource and a number of short deletions of the respective resource. The plurality of resources are ranked based on the respective LACTRs for the plurality of resources. The ranking of the plurality of resources are provided.	10-04-2012

Bingrui Yang, Mountain View, CA US

Patent application number	Description	Published
20130154998	Electronic Device with Noise-Cancelling Force Sensor - An electronic device may have a housing in which components such as a display are mounted. A strain gauge may be mounted on a layer of the display such as a cover layer or may be mounted on a portion of the housing or other support structure. The layer of material on which the strain gauge is mounted may be configured to flex in response to pressure applied by a finger of a user. The strain gauge may serve as a button for the electronic device or may form part of other input circuitry. A differential amplifier and analog-to-digital converter circuit may be used to gather and process strain gauge signals. The strain gauge may be formed form variable resistor structures that make up part of a bridge circuit that is coupled to the differential amplifier. The bridge circuit may be configured to reduce the impact of capacitively coupled noise.	06-20-2013

Cara S. Yang, Mountain View, CA US

Patent application number	Description	Published
20130329897	ELECTRONIC AUDIO DEVICE TO DETERMINE MATCHING AND NON-MATCHING SPEAKERS - An electronic audio system that determines matching and non-matching speakers is disclosed. The electronic audio system includes a first speaker; a second speaker; and a comparator circuit. The comparator circuit is coupled to the first speaker and the second speaker to receive an input signal from both the first and second speaker. The comparator circuit is configured to determine if the first speaker and the second speaker are matching speakers or non-matching speakers, in which, the first and second speakers are matching speakers if they are common vendor speakers. Other embodiments are also described and claimed.	12-12-2013
20130329916	GROUNDING CIRCUIT FOR ALTERNATE AUDIO PLUG DESIGNS - Circuits, methods, and apparatus for grounding contacts in an audio jack. One example may provide a driver, such as a charge pump, driving a first depletion mode transistor coupled between a first contact in an audio jack and ground, and a second depletion mode transistor coupled between a second contact in the audio jack and ground. The first depletion mode transistor and second depletion mode transistor may be p-channel transistors or n-channel transistors.	12-12-2013
20140093103	INCREASING GROUND NOISE REJECTION IN AUDIO SYSTEMS - An audio source device has an audio connector to which an external load can be connected. An audio signal is amplified and then driven through the connector, wherein the amplification process uses feedback from the return pin of the connector. The return pin is directly connected to a ground break resistor circuit. The ground break resistor circuit is connected between the return pin of the audio connector and circuit ground. A determination is made as to whether the connected external load has a low impedance or a high impedance. When a low impedance load is detected, such as a headset, the ground break resistor circuit is essentially short-circuited. When a high impedance load is detected, the ground break resistor circuit is maintained and its value is set in accordance with the detected load. Other embodiments are also described.	04-03-2014

Cheng-Han Yang, Mountain View, CA US

Patent application number	Description	Published
20140154529	MAGNETORESISTIVE SENSOR FOR A MAGNETIC STORAGE SYSTEM READ HEAD, AND FABRICATION METHOD THEREOF - A magnetic read transducer including a magnetoresistive sensor is described, as well as a fabrication method thereof. The magnetoresistive sensor includes a cap layer overlaying a free layer. The cap layer is situated with a first thickness to absorb boron from the free layer. The magnetoresistive sensor is annealed, and boron is diffused from the free layer and absorbed by the cap layer, improving the magnetic performance of the free layer. The cap layer thickness is then reduced to a second thickness, thereby reducing the shield-to-shield (SS) stack spacing of the magnetoresistive sensor and allowing for increased areal recording density.	06-05-2014

Dali Yang, Mountain View, CA US

Patent application number	Description	Published
20080265996	Digital Hybrid Mode Power Amplifier System - A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The power amplifier characteristics such as variation of linearity and asymmetric distortion of the amplifier output signal are monitored by the narrowband feedback path and controlled by the adaptation algorithm in a digital module. Therefore, the present invention could compensate the nonlinearities as well as memory effects of the power amplifier systems and also improve performances, in terms of power added efficiency, adjacent channel leakage ratio and peak-to-average power ratio. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.	10-30-2008
20090085658	ANALOG POWER AMPLIFIER PREDISTORTION METHODS AND APPARATUS - An embodiment of the invention is a predistortion approach to linearize a power amplifier by using one or more analog multiplier(s) and a DSP-based processor. For the analog embodiment, the inherent nature of the analog circuitries allows digital predistortion processing structured directly at the RF band, and enables a single power amplifier to support multi-modulation schemes, multi-carriers and multi-channels. As a result, the predistortion architecture is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems. The wireless system performance can be improved and upgraded just by using the new PA module rather than change or rebuild new subsystem in existing base station. The analog embodiment can also mix and match its analog multipliers with other analog components such as phase splitters, phase shifters, attenuators, filters, couplers, mixers, low-noise amplifiers, buffers, envelope detectors, and etc., to provide additional features.	04-02-2009
20090096521	POWER AMPLIFIER PREDISTORTION METHODS AND APPARATUS USING ENVELOPE AND PHASE DETECTOR - An embodiment of the invention is a predistortion approach to linearize a power amplifier without frequency conversion of the RF signals by using envelope and phase detectors to detect the error to be corrected, and then one or more analog multiplier(s) and a DSP-based processor. For the analog embodiment, the inherent nature of the analog circuitries allows digital predistortion processing structured directly at the RF band, and enables a single power amplifier to support multi-modulation schemes, multi-carriers and multi-channels. As a result, the predistortion architecture is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems. The wireless system performance can be improved and upgraded just by using the new PA module rather than change or rebuild new subsystem in existing base station. The analog embodiment can also mix and match its analog multipliers with other analog components such as phase splitters, phase shifters, attenuators, filters, couplers, mixers, low-noise amplifiers, buffers, envelope detectors, and etc., to provide additional features.	04-16-2009
20120135695	HIGH EFFICIENCY LINEARIZATION POWER AMPLIFIER FOR WIRELESS COMMUNICATION - A predistortion system for linearizing the output of a power amplifier includes a first signal representative of an RF modulated signal and a feedback signal representative of nonlinear characteristics of a power amplifier. The system also includes a predistortion controller, comprising at least one lookup table, adapted to receive the first signal and the feedback signal and to generate a correction factor for correcting the nonlinear characteristics of the power amplifier and combining logic which combines the RF modulated signal with a signal corresponding to the correction factor and supplies it to the power amplifier to linearize the output of the power amplifier.	05-31-2012
20130147550	Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus - An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.	06-13-2013
20130243124	SYSTEM AND METHOD FOR DIGITAL MEMORIZED PREDISTORTION FOR WIRELESS COMMUNICATION - An embodiment of the invention is a system for signal processing in preparation for wireless transmission, the wireless transmission being from a portable wireless communication device and including use of a power amplifier having nonlinear characteristics. The system includes memory for storing digitally-indexed information. The digitally-indexed information models nonlinear characteristics of the power amplifier, and the digitally-indexed information is stored prior to processing of a first signal that reflects information to be communicated. The system further includes first logic, configured to accept the first signal and to retrieve, based on the first signal, a portion of the digitally-indexed information stored in the memory, and second logic, configured to generate a second signal based on the portion of the digitally-accessed information and on the first signal. The second signal pre-compensates for the nonlinear characteristics of the power amplifier, and the second signal is for wireless transmission based on the second signal.	09-19-2013
20140179248	HIGH EFFICIENCY LINEARIZATION POWER AMPLIFIER FOR WIRELESS COMMUNICATION - A predistortion system for linearizing the output of a power amplifier includes a first signal representative of an RF modulated signal and a feedback signal representative of nonlinear characteristics of a power amplifier. The system also includes a predistortion controller, comprising at least one lookup table, adapted to receive the first signal and the feedback signal and to generate a correction factor for correcting the nonlinear characteristics of the power amplifier and combining logic which combines the RF modulated signal with a signal corresponding to the correction factor and supplies it to the power amplifier to linearize the output of the power amplifier.	06-26-2014
20140306762	SYSTEM AND METHOD FOR DIGITAL MEMORIZED PREDISTORTION FOR WIRELESS COMMUNICATION - A power amplifier system includes an input operable to receive an original value that reflects information to be communicated and an address data former operable to generate a digital lookup table key. The power amplifier system also includes a predistortion lookup table coupled to the address data former and a power amplifier having an output and coupled to the predistortion lookup table. The power amplifier system further includes a feedback loop providing a signal associated with the output of the power amplifier to the predistortion lookup table and a switch disposed in the feedback loop and operable to disconnect the predistortion lookup table from the output of the power amplifier.	10-16-2014
20140327481	DIGITAL HYBRID MODE POWER AMPLIFIER SYSTEM - A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The power amplifier characteristics such as variation of linearity and asymmetric distortion of the amplifier output signal are monitored by the narrowband feedback path and controlled by the adaptation algorithm in a digital module. Therefore, the present invention could compensate the nonlinearities as well as memory effects of the power amplifier systems and also improve performances, in terms of power added efficiency, adjacent channel leakage ratio and peak-to-average power ratio. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.	11-06-2014
20150326349	SYSTEM AND METHOD FOR DIGITAL MEMORIZED PREDISTORTION FOR WIRELESS COMMUNICATION - A power amplifier system includes an input operable to receive an original value that reflects information to be communicated and an address data former operable to generate a digital lookup table key. The power amplifier system also includes a predistortion lookup table coupled to the address data former and a power amplifier having an output and coupled to the predistortion lookup table. The power amplifier system further includes a feedback loop providing a signal associated with the output of the power amplifier to the predistortion lookup table and a switch disposed in the feedback loop and operable to disconnect the predistortion lookup table from the output of the power amplifier.	11-12-2015
20150333710	HIGH EFFICIENCY LINEARIZATION POWER AMPLIFIER FOR WIRELESS COMMUNICATION - A predistortion system for linearizing the output of a power amplifier includes a first signal representative of an RF modulated signal and a feedback signal representative of nonlinear characteristics of a power amplifier. The system also includes a predistortion controller, comprising at least one lookup table, adapted to receive the first signal and the feedback signal and to generate a correction factor for correcting the nonlinear characteristics of the power amplifier and combining logic which combines the RF modulated signal with a signal corresponding to the correction factor and supplies it to the power amplifier to linearize the output of the power amplifier.	11-19-2015
20160036394	POWER AMPLIFIER TIME-DELAY INVARIANT PREDISTORTION METHODS AND APPARATUS - An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.	02-04-2016

Demao Yang, Mountain View, CA US

Patent application number	Description	Published
20080292605	Materials for stimulation of hematopoiesis by ex vivo activated cells - A protocol of activating and administering human blood cells so that bone marrow histology and/or blood cell counts of patients suffering from a plastic anemia approach normal. The protocol includes culturing the blood cells in the presence of a cytokine and an ionophore. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.	11-27-2008

James Tsung-Tai Yang, Mountain View, CA US

Patent application number	Description	Published
20110058627	USE OF RDS DATA TO SELECT MATCHING NETWORK - Devices and methods for dynamically selecting a matching network for an antenna are provided. In one example, an electronic device capable of selecting such a matching network may include an antenna, several selectable matching networks, a radio receiver, and matching network control circuitry. The radio receiver may couple to the antenna via one of the selectable matching networks to receive a radio signal with both an analog and digital component. The matching network control circuitry may select the matching network from among the several selectable matching networks based at least in part on a characteristic of the digital component of the radio signal.	03-10-2011

Jia Yang, Mountain View, CA US

Patent application number	Description	Published
20120135695	HIGH EFFICIENCY LINEARIZATION POWER AMPLIFIER FOR WIRELESS COMMUNICATION - A predistortion system for linearizing the output of a power amplifier includes a first signal representative of an RF modulated signal and a feedback signal representative of nonlinear characteristics of a power amplifier. The system also includes a predistortion controller, comprising at least one lookup table, adapted to receive the first signal and the feedback signal and to generate a correction factor for correcting the nonlinear characteristics of the power amplifier and combining logic which combines the RF modulated signal with a signal corresponding to the correction factor and supplies it to the power amplifier to linearize the output of the power amplifier.	05-31-2012
20130147550	Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus - An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.	06-13-2013
20130243124	SYSTEM AND METHOD FOR DIGITAL MEMORIZED PREDISTORTION FOR WIRELESS COMMUNICATION - An embodiment of the invention is a system for signal processing in preparation for wireless transmission, the wireless transmission being from a portable wireless communication device and including use of a power amplifier having nonlinear characteristics. The system includes memory for storing digitally-indexed information. The digitally-indexed information models nonlinear characteristics of the power amplifier, and the digitally-indexed information is stored prior to processing of a first signal that reflects information to be communicated. The system further includes first logic, configured to accept the first signal and to retrieve, based on the first signal, a portion of the digitally-indexed information stored in the memory, and second logic, configured to generate a second signal based on the portion of the digitally-accessed information and on the first signal. The second signal pre-compensates for the nonlinear characteristics of the power amplifier, and the second signal is for wireless transmission based on the second signal.	09-19-2013
20140179248	HIGH EFFICIENCY LINEARIZATION POWER AMPLIFIER FOR WIRELESS COMMUNICATION - A predistortion system for linearizing the output of a power amplifier includes a first signal representative of an RF modulated signal and a feedback signal representative of nonlinear characteristics of a power amplifier. The system also includes a predistortion controller, comprising at least one lookup table, adapted to receive the first signal and the feedback signal and to generate a correction factor for correcting the nonlinear characteristics of the power amplifier and combining logic which combines the RF modulated signal with a signal corresponding to the correction factor and supplies it to the power amplifier to linearize the output of the power amplifier.	06-26-2014
20140306762	SYSTEM AND METHOD FOR DIGITAL MEMORIZED PREDISTORTION FOR WIRELESS COMMUNICATION - A power amplifier system includes an input operable to receive an original value that reflects information to be communicated and an address data former operable to generate a digital lookup table key. The power amplifier system also includes a predistortion lookup table coupled to the address data former and a power amplifier having an output and coupled to the predistortion lookup table. The power amplifier system further includes a feedback loop providing a signal associated with the output of the power amplifier to the predistortion lookup table and a switch disposed in the feedback loop and operable to disconnect the predistortion lookup table from the output of the power amplifier.	10-16-2014
20150326349	SYSTEM AND METHOD FOR DIGITAL MEMORIZED PREDISTORTION FOR WIRELESS COMMUNICATION - A power amplifier system includes an input operable to receive an original value that reflects information to be communicated and an address data former operable to generate a digital lookup table key. The power amplifier system also includes a predistortion lookup table coupled to the address data former and a power amplifier having an output and coupled to the predistortion lookup table. The power amplifier system further includes a feedback loop providing a signal associated with the output of the power amplifier to the predistortion lookup table and a switch disposed in the feedback loop and operable to disconnect the predistortion lookup table from the output of the power amplifier.	11-12-2015
20150333710	HIGH EFFICIENCY LINEARIZATION POWER AMPLIFIER FOR WIRELESS COMMUNICATION - A predistortion system for linearizing the output of a power amplifier includes a first signal representative of an RF modulated signal and a feedback signal representative of nonlinear characteristics of a power amplifier. The system also includes a predistortion controller, comprising at least one lookup table, adapted to receive the first signal and the feedback signal and to generate a correction factor for correcting the nonlinear characteristics of the power amplifier and combining logic which combines the RF modulated signal with a signal corresponding to the correction factor and supplies it to the power amplifier to linearize the output of the power amplifier.	11-19-2015
20160036394	POWER AMPLIFIER TIME-DELAY INVARIANT PREDISTORTION METHODS AND APPARATUS - An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.	02-04-2016

Jin Yang, Mountain View, CA US

Patent application number	Description	Published
20130109738	Control of Cardiac Growth, Differentiation and Hypertrophy	05-02-2013

Jungsook Yang, Mountain View, CA US

Patent application number	Description	Published
20160110121	RESOURCE RESERVATION FOR STORAGE SYSTEM METADATA UPDATES - It is determined that a first set of one or more blocks associated with a file system are to be freed. Each of the first set of blocks is associated with a block identifier. In response to a determination that the first set of blocks is to be freed, it is determined that a first log has been allocated an insufficient number of data blocks to store the block identifiers that are associated with the first set of blocks. In response to a determination that the first log has been allocated an insufficient number of data blocks, one or more data blocks are allocated to the first log. It is indicated that one or more block identifiers are to be removed from the first log and added to a second log. It is indicated that metadata associated with a second set of one or more blocks is to be updated.	04-21-2016

Ke Yang, Mountain View, CA US

Patent application number	Description	Published
20110196861	Propagating Information Among Web Pages - Web pages of a Website may be processed to improve search results. For example, information likely to pertain to more than just the Web page it is directly associated with may be identified. One or more other, related, Web pages that such information is likely to pertain to is also identified. The identified information is associated with the identified other Web page(s) and this association is saved in a way to affect a search result score of the Web page(s).	08-11-2011

Mark C. Yang, Mountain View, CA US

Patent application number	Description	Published
20080208165	METHODS, SYSTEMS, AND KITS FOR IMPLANTING ARTICLES - Methods, systems, and kits for subcutaneously implanting articles, such as drug inserts and reservoirs. The methods rely on percutaneously forming a tissue tract and radially dilating the tract to a diameter which permits introduction of the article. By fully expanding the lumenal diameter of the tissue tract prior to introduction of the article, damage to the article resulting from passage through a partially expanded tissue tract can be avoided. In the exemplary embodiment, a radially expandable sleeve is first percutaneously introduced to the subcutaneous target site. An assembly of a cannula and dilator is then passed through the sleeve, effecting radial expansion. The dilator is removed and the article is then introduced through a lumen of the cannula.	08-28-2008
20110144622	METHODS, SYSTEMS, AND KITS FOR IMPLANTING ARTICLES - Methods, systems, and kits for subcutaneously implanting articles, such as drug inserts and reservoirs. The methods rely on percutaneously forming a tissue tract and radially dilating the tract to a diameter which permits introduction of the article. By fully expanding the lumenal diameter of the tissue tract prior to introduction of the article, damage to the article resulting from passage through a partially expanded tissue tract can be avoided. In the exemplary embodiment, a radially expandable sleeve is first percutaneously introduced to the subcutaneous target site. An assembly of a cannula and dilator is then passed through the sleeve, effecting radial expansion. The dilator is removed and the article is then introduced through a lumen of the cannula.	06-16-2011

Minxian Max Yang, Mountain View, CA US

Patent application number	Description	Published
20130307662	NEGATIVE DIFFERENTIAL RESISTANCE DEVICE - Apparatus and methods related to negative differential resistance (NDR) are provided. An NDR device includes a spaced pair of electrodes and at least two different materials disposed there between. One of the two materials is characterized by negative thermal expansion, while the other material is characterized by positive thermal expansion. The two materials are further characterized by distinct electrical resistivities. The NDR device is characterized by a non-linear electrical resistance curve that includes a negative differential resistance range. The NDR device operates along the curve in accordance with an applied voltage across the pair of electrodes.	11-21-2013

Nian Niles Yang, Mountain View, CA US

Patent application number	Description	Published
20140115230	Flash Memory with Data Retention Partition - A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data.	04-24-2014
20140126292	Flash Memory with Data Retention Bias - Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die.	05-08-2014
20140160842	Adaptive Operation of Multi Level Cell Memory - A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode.	06-12-2014
20140173172	SYSTEM AND METHOD TO UPDATE READ VOLTAGES IN A NON-VOLATILE MEMORY IN RESPONSE TO TRACKING DATA - A method includes reading a representation of tracking data from at least a portion of a non-volatile memory. The method further includes adjusting a read voltage based on a comparison between a number of bits in tracking data as compared to a count of bits in the representation of the tracking data.	06-19-2014
20140173382	INSPECTION OF NON-VOLATILE MEMORY FOR DISTURB EFFECTS - A method performed in a data storage device including a non-volatile memory includes reading a representation of data, the representation corresponding to one or more selected states of storage elements of a group of storage elements of the non-volatile memory. The method includes, in response to a count of errors in the representation of the data exceeding a threshold, scheduling a remedial action to be performed on the group of storage elements.	06-19-2014
20140281685	PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.	09-18-2014
20140281766	PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.	09-18-2014
20140293699	High Endurance Nonvolatile Memory - A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks.	10-02-2014
20140321202	DEFECTIVE BLOCK MANAGEMENT - In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.	10-30-2014
20150046770	SENSING PARAMETER MANAGEMENT IN NON-VOLATILE MEMORY STORAGE SYSTEM TO COMPENSATE FOR BROKEN WORD LINES - Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line.	02-12-2015
20150058530	SMART DYNAMIC WEAR BALANCING BETWEEN MEMORY POOLS - A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.	02-26-2015
20150071008	Systems And Methods For Read Disturb Management In Non-Volatile Memory - Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.	03-12-2015
20150085571	UPDATING READ VOLTAGES - A data storage device includes a controller that is configured to determine a first read voltage for a first page of a non-volatile memory (e.g., a lower page of a Multi-Level Cell flash memory device). The controller is also configured to determine a second read voltage for a second page (e.g., an upper page) of the non-volatile memory by applying an offset value to the first read voltage. The controller is also configured to store data identifying the first read voltage and the second read voltage.	03-26-2015
20150089324	METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.	03-26-2015
20150089325	METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.	03-26-2015
20150143026	TEMPERATURE BASED FLASH MEMORY SYSTEM MAINTENANCE - A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.	05-21-2015
20150348649	BIT ERROR RATE MAPPING IN A MEMORY SYSTEM - A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.	12-03-2015

Niles Yang, Mountain View, CA US

Patent application number	Description	Published
20150149693	Targeted Copy of Data Relocation - In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable. Subsequent reads of the relocated data directed to binary cache.	05-28-2015
20150318055	System Method and Apparatus for Screening a Memory System - A system and method of writing data to a memory block includes receiving user data in a memory controller, the user data to be written to the memory block. The user data is first written to a buffer in the memory controller. A screening pattern is written to at least one screening column in the memory block and a first memory integrity test is performed. The first memory integrity test includes reading screening column data from the at least one screening column and comparing the screening column data read from the at least one screening column to the screening pattern. The user data is written to at least one user data column in the memory block when the screening column data read from the at least one screening column matches the screening pattern in the first memory integrity test.	11-05-2015
20150339195	METHOD AND SYSTEM FOR SECURE SYSTEM RECOVERY - Apparatus and methods implemented therein are disclosed for recovery of information stored in non-volatile memory of embedded and external solid-state memory devices. The apparatus comprises a memory system. The memory system has a non-volatile memory and a memory controller. The memory controller is coupled to the non-volatile memory. The memory controller is also coupled to a memory interface. The memory controller searches the non-volatile memory to locate initialization information required to initialize the memory controller. The memory controller, in response to failing to successfully locate or execute the initialization information, is configured to transmit an indication via the memory interface.	11-26-2015
20150347228	METHOD AND APPARATUS FOR RELOCATING DATA IN NON-VOLATILE MEMORY - Apparatus and methods implemented therein are disclosed for relocating data stored in pages of a non-volatile memory. The number of memory chunks with invalid data in an SLC type first page is determined and if the number is above a first threshold and above a second threshold, a bit error rate (BER) for the valid data in the set of memory chunks of the first page is compared with a first BER threshold. If the BER is below the first BER threshold, an error correcting code (ECC) for valid data in a set of memory chunks of a second page is computed and the invalid data of the first page with valid data is replaced with valid data from the second page and the computed ECC. The valid data of the first and second page is relocated to a third page.	12-03-2015
20160077903	Selective Sampling of Data Stored in Nonvolatile Memory - Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts.	03-17-2016
20160098216	SYSTEM AND METHOD FOR REFRESHING DATA IN A MEMORY DEVICE - Systems, apparatuses, and methods are provided that refresh data in a memory. Data is programmed into the memory. After which, part or all of the data may be refreshed. The refresh of the data may be different from the initial programming of the data in one or more respects. For example, the refresh of the data may include fewer steps than the programming of the data and may be performed without erasing a section of memory. Further, the refresh of the data may be triggered in one of several ways. For example, after programming the data, the data may be analyzed for errors. Based on the number of errors found, the data may be refreshed.	04-07-2016

Qingxiong Yang, Mountain View, CA US

Patent application number	Description	Published
20100253684	Methods for obtaining a three-band intrinsic image from a single input image - Various embodiments of the present invention related to methods for obtaining shadow invariant and shadow-shading invariant images from a single camera image taken with a narrow-band camera sensor and assuming Plankian illuminating conditions.	10-07-2010

Richard J. Yang, Mountain View, CA US

Patent application number	Description	Published
20090170538	Mobile Location Sharing System - A mobile location sharing system comprising: enabling a sender wireless device to send a payload including a location descriptor and a list of target identifiers to a group of targets; identifying a preferred communication mode for each in the group of targets; selecting a transmission format for the preferred communication mode; and sending the location descriptor in the transmission format selected for each in the group of targets for audio-visual output.	07-02-2009

Richard Jingwen Yang, Mountain View, CA US

Patent application number	Description	Published
20100005135	GENERAL PURPOSE MOBILE LOCATION-BLOGGING SYSTEM - A method for operating a general purpose mobile location-blogging system includes receiving a location-blog request having multimedia data at a server; managing a location-blog entry parameter with the location-blog request; sending the location-blog entry parameter from the server for selecting the location-blog entry parameter at a client, and displaying the location-blog entry parameter that has been selected with a multimedia display interface of the client.	01-07-2010
20130096821	NAVIGATION SYSTEM WITH NON-NATIVE DYNAMIC NAVIGATOR MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a navigation system includes: receiving a destination; generating a route to the destination; and generating a non-native dynamic navigation based on the route for displaying on a device.	04-18-2013
20150338219	NAVIGATION SYSTEM WITH COMMUNICATION MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a navigation system includes: identifying a navigational context for representing a user; determining a participant identification based on the navigational context for representing a participant, the participant identification including a familiarity rating; and generating a communication channel with a control unit during a navigation session based on the navigational context for communicating a message between the user and the participant independent of the familiarity rating.	11-26-2015

Sheng Yang, Mountain View, CA US

Patent application number	Description	Published
20150208826	DISPLAY SYSTEMS AND METHODS - A display system and method for displaying a product is disclosed. The system may include a display stem and a retainer for holding the product. The retainer may include a bracket and a retainer body having a substantially smooth surface. The display stem may include a recess for receiving at least a portion of the retainer body. The retainer may be oriented on top of the display stem in one or more predetermined positions through the use of magnetic forces. The retainer may be returned to and held on top of the display stem using a retaining cable. The retainer body and recess may include charging contacts for delivering power to a product held by the retainer when the retainer body is received within the recess.	07-30-2015
20160058206	TABLE DISPLAY SYSTEM - A display apparatus, such as a table, for display consumer products, such as electronic devices, is disclosed. The table may include a display cavity for displaying products. The display cavity may include a transparent glass panel defining a top portion thereof so as to allow consumers to view products housed within the display cavity. The table may include a lighting system configured to illuminate at least a portion of the display cavity. The table may also include a cooling system for maintaining or modifying the temperature within the display cavity. A rotatable display panel defining at least a portion of the bottom of display cavity may rotate from the bottom of the table to allow a user can access the products within the display cavity.	03-03-2016
20160064995	FIXTURES FOR DISPLAYING PRODUCTS - A display apparatus, such as a table, for display consumer products, such as electronic devices, is disclosed. The table may include a display cavity for displaying products. The display cavity may include a transparent glass panel defining a top portion thereof so as to allow consumers to view products housed within the display cavity. A display fixture for holding a consumer product with the display cavity is disclosed. A kit for aligning a plurality of nodes on the display panel is also disclosed. A DC-to-DC converter that can receive a DC input voltage via a first standard receptacle connector, convert the DC input voltage to a DC output voltage using regulator circuitry and provide the DC output voltage at a second standard receptacle connector is also disclosed. The DC-to-DC converter can include a compact, cosmetic, minimalist housing for containing a space-efficient printed circuit board that includes the regulator circuitry.	03-03-2016

Suwen Yang, Mountain View, CA US

Patent application number	Description	Published
20130135017	SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY - The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.	05-30-2013
20140312982	CONTINUOUS PHASE ADJUSTMENT BASED ON INJECTION LOCKING - A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.	10-23-2014
20140314191	DISTRIBUTED PHASE-CORRECTION CIRCUIT - A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.	10-23-2014

Tong Yang, Mountain View, CA US

Patent application number	Description	Published
20140244423	DYNAMIC RANKING OF PRODUCTS FOR PRESENTATION TO USERS - The disclosed embodiments provide a system that processes user data. During operation, the system obtains a set of ranking engines for a set of products and selects a ranking engine from the set of ranking engines. Next, the system provides the user data for a user to the ranking engine and obtains, in response to the provided user data, a list of ranked products for the user from the ranking engine. Finally, the system provides the products to the user based on the list to facilitate selection of one or more of the products by the user.	08-28-2014
20140244428	DYNAMIC PRESENTATION OF RECOMMENDED PRODUCTS TO USERS - The disclosed embodiments provide a system that facilitates interaction with a user. During operation, the system obtains a set of features associated with one or more products recommended for the user. Next, the system provides an editor for modifying the features and obtains one or more customizations to the features through the editor. Finally, the system displays the features and the customizations to the user without requiring modification to source code associated with displaying the features to the user.	08-28-2014

Tong (bruce) Yang, Mountain View, CA US

Patent application number	Description	Published
20140324569	METHOD AND SYSTEM TO MEDIATE SELECTION OF CHOICE PRESENTATION MODELS - A method and system to mediate selection of choice presentation models are described. A models mediator, implemented using software, hardware or both, may be configured to exercise different choice presentation models, collect and analyze information with respect to how well each model performed in succeeding to convince a respective user to purchase one of the presented subscription plans, and determine how frequently each model should be used to generate a presentation of subscription choices.	10-30-2014

Wen Yang, Mountain View, CA US

Patent application number	Description	Published
20110105351	Multiplex branched-chain DNA assays - Methods of detecting two or more nucleic acids in a multiplex branched-chain DNA assay are provided. Different nucleic acids are captured through cooperative hybridization events on different, identifiable subsets of particles or at different selected positions on a spatially addressable solid support. Compositions, kits, and systems related to the methods are also described.	05-05-2011
20110171644	Multiplex capture of nucleic acids - Methods of capturing two or more nucleic acids simultaneously from a single sample are provided. Different nucleic acids are captured through cooperative hybridization events on different subsets of particles or at different selected positions on a spatially addressable solid support. Methods of capturing one or more long nucleic acids and methods of capturing one or more nucleic acid for sequencing are also provided. Compositions, kits, and systems related to the methods are also described.	07-14-2011
20130303392	Multiplex branched-chain DNA assays - Methods of detecting two or more nucleic acids in a multiplex branched-chain DNA assay are provided. Different nucleic acids are captured through cooperative hybridization events on different, identifiable subsets of particles or at different selected positions on a spatially addressable solid support. Compositions, kits, and systems related to the methods are also described.	11-14-2013
20140194296	Multiplex Capture of Nucleic Acids - Methods of capturing two or more nucleic acids simultaneously from a single sample are provided. Different nucleic acids are captured through cooperative hybridization events on different subsets of particles or at different selected positions on a spatially addressable solid support. Methods of capturing one or more long nucleic acids and methods of capturing one or more nucleic acid for sequencing are also provided. Compositions, kits, and systems related to the methods are also described.	07-10-2014

Xin Yang, Mountain View, CA US

Patent application number	Description	Published
20150085668	Discovering Stable Routes in Wireless Networks - A method discovers routes for forwarding packets from source nodes (sources) to sink nodes (sinks) in a wireless network, wherein some neighboring sources act as relay nodes. Each source measures a rate of receiving control messages from each neighboring node. Then, the data packets are forwarded from a particular source to the sink via the neighboring nodes having a lowest rate.	03-26-2015

Zhimou Yang, Mountain View, CA US

Patent application number	Description	Published
20100093084	METHOD FOR CREATING INTRACELLULAR ARTIFICIAL NANOSTRUCTURES IN SITU - A method of creating intracellular artificial nanostructures in situ, which employees a chemical precursor. The precursor does not self-assemble due to the presence of a cleavable motif linked to it. When the precursor comes inside live cells by an uptaking mechanism on the cell membrane, the cleavable motif is then to be removed by an enzymatic action of a first enzyme. Without the cleavable motif, the precursor now engages in a self-assembling process to form nanostructures within the live cells, which may cause formation of a hydrogel. Furthermore, the self-assembling process can be made reversible by employing a second enzyme which puts the cleavable motif back to the precursor, whereby dissolving the nanostructures into solution.	04-15-2010

Zishuang Yang, Mountain View, CA US

Patent application number	Description	Published
20140214737	Selecting Social Networking System User Information for Display Via a Timeline Interface - The invention provides a display interface in a social networking system that enables the presentation of information related to a user in a timeline or map view. The system accesses information about a user of a social networking system, including both data about the user and social network activities related to the user. The system then selects one or more of these pieces of data and/or activities from a certain time period and gathers them into timeline units based on their relatedness and their relevance to users. These timeline units are ranked by relevance to the user, and are used to generate a timeline or map view for the user containing visual representations of the timeline units organized by location or time. The timeline or map view is then provided to other users of the social networking system that wish to view information about the user.	07-31-2014

Zizhuang Yang, Mountain View, CA US

Patent application number	Description	Published
20130073984	Displaying Social Networking System User Information Via a Timeline Interface - The invention provides a display interface in a social networking system that enables the presentation of information related to a user in a timeline or map view. The system accesses information about a user of a social networking system, including both data about the user and social network activities related to the user. The system then selects one or more of these pieces of data and/or activities from a certain time period and gathers them into timeline units based on their relatedness and their relevance to users. These timeline units are ranked by relevance to the user, and are used to generate a timeline or map view for the user containing visual representations of the timeline units organized by location or time. The timeline or map view is then provided to other users of the social networking system that wish to view information about the user.	03-21-2013