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| 20120181669 | FRAME CELL FOR SHOT LAYOUT FLEXIBILITY - A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout. | 07-19-2012 |
| 20130052813 | METHOD AND STRUCTURE FOR ADVANCED SEMICONDUCTOR CHANNEL SUBSTRATE MATERIALS - Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material. | 02-28-2013 |
| 20130171336 | WAFER PROCESSING METHOD AND SYSTEM USING MULTI-ZONE CHUCK - In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones. | 07-04-2013 |
| 20130210173 | Multiple Zone Temperature Control for CMP - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed. | 08-15-2013 |
| 20130210323 | CMP Pad Cleaning Apparatus - The present disclosure relates to a two-phase cleaning element that enhances polishing pad cleaning so as to prevent wafer scratches and contamination in chemical mechanical polishing (CMP) processes. In some embodiments, the two-phase pad cleaning element comprises a first cleaning element and a second cleaning element configured to successively operate upon a section of a CMP polishing pad. The first cleaning element comprises a megasonic cleaning jet configured to utilize cavitation energy to dislodge particles embedded in the CMP polishing pad without damaging the surface of the polishing pad. The second cleaning element is configured to apply a high pressure mist, comprising two fluids, to remove by-products from the CMP polishing pad. By using megasonic cleaning to dislodge embedded particles a two-fluid mist to flush away by-products (e.g., including the dislodged embedded particles), the two-phase pad cleaning element enhances polishing pad cleaning. | 08-15-2013 |
| 20130217306 | CMP Groove Depth and Conditioning Disk Monitoring - Some embodiments relate to a chemical mechanical polishing (CMP) system. The CMP system includes a polishing pad having a polishing surface, and a wafer carrier to retain a wafer proximate to the polishing surface during polishing. A motor assembly rotates the polishing pad and concurrently rotates the wafer during polishing of the wafer. A conditioning disk has a conditioning surface that is in frictional engagement with the polishing surface during polishing. A torque measurement element measures a torque exerted by the motor assembly during polishing. A condition surface analyzer determines a surface condition of the conditioning surface or the polishing surface based on the measured torque. Other systems and methods are also disclosed. | 08-22-2013 |
| 20130244552 | MANUFACTURE AND METHOD OF MAKING THE SAME - A manufacture includes a substrate, a reinforcement layer over the substrate, and abrasive particles over the substrate. The abrasive particles are partially buried in the reinforcement layer. Upper tips of the abrasive particles are substantially coplanar. | 09-19-2013 |
| 20130264498 | SYSTEM AND METHOD OF ION NEUTRALIZATION WITH MULTIPLE-ZONED PLASMA FLOOD GUN - An apparatus comprises a plasma flood gun for neutralizing a positive charge buildup on a semiconductor wafer during a process of ion implantation using an ion beam. The plasma flood gun comprises more than two arc chambers, wherein each arc chamber is configured to generate and release electrons into the ion beam in a respective zone adjacent to the semiconductor wafer. | 10-10-2013 |
| 20130270454 | SYSTEM AND METHOD OF ION BEAM SOURCE FOR SEMICONDUCTOR ION IMPLANTATION - An apparatus comprises an ionization chamber for providing ions during a process of ion implantation, and an electron beam source device inside the ionization chamber. The electron beam source device comprises a field emission array having a plurality of emitters for generating electrons in vacuum under an electric field. | 10-17-2013 |
| 20130280922 | METHODS FOR FABRICATING AND ORIENTING SEMICONDUCTOR WAFERS - A method of orienting a semiconductor wafer. The method includes rotating a wafer about a central axis; exposing a plurality of edge portions of the rotating wafer to light having a predetermined wavelength from one or more light sources; detecting a subsurface mark in one of the plurality of edge portions of the rotating wafer; and orienting the wafer using the detected subsurface mark as a reference. | 10-24-2013 |
| 20130295753 | ION BEAM DIMENSION CONTROL FOR ION IMPLANTATION PROCESS AND APPARATUS, AND ADVANCED PROCESS CONTROL - A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate. | 11-07-2013 |
| 20140095083 | Method Of Identifying Airborne Molecular Contamination Source - The present disclosure provides a method of identifying an airborne molecular contamination (AMC) leaking source in a fab. The method includes distributing a sensor in the fab, executing a forward computational fluid dynamics (CFD) simulation of an air flow in the fab, setting an inversed modeling of the forward CFD simulation of the air flow in the fab, building up a database of a spatial response probability distribution matrix of the sensor using an AMC measurement data in the fab, and identifying the AMC leaking source using the database of the spatial response probability distribution matrix of the sensor. | 04-03-2014 |
| 20140148008 | MULTI-POINT CHEMICAL MECHANICAL POLISHING END POINT DETECTION SYSTEM AND METHOD OF USING - A wafer polishing system including a platen configured to rotate in a first direction, and a polishing head configured to hold a wafer, the polishing head configured to rotate in a second direction. The wafer polishing system further includes an optical sensing system configured to detect a thickness of the wafer at a first location on the platen and a second location on the platen. A first distance from a center of the platen to the first location is different than a second distance from the center of the platen to the second location. | 05-29-2014 |
| 20140154848 | N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer. | 06-05-2014 |
| 20140158172 | SYSTEM AND METHOD OF CLEANING FOUP - A system for cleaning a container such as semiconductor wafer carrier includes a housing, a cleaning unit in the housing, an analyzing unit within the housing, and a vacuum unit within the housing. The cleaning unit comprises a cleaning chamber, and is configured to spray a cleaning medium into the container in the cleaning chamber and dry the container. The analyzing unit is configured to analyze air inside the container coming out of the cleaning chamber, and provide a testing result for each ingredient of possible airborne molecular contamination (AMC) and humidity. The vacuum unit comprises a vacuum chamber configured to apply vacuum onto a container when the testing result for an ingredient is higher than a respective threshold. | 06-12-2014 |
| 20140159243 | Metal Conductor Chemical Mechanical Polish - The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment. | 06-12-2014 |
| 20140166055 | APPARATUS AND METHOD OF CLEANING WAFERS - An apparatus for cleaning wafers includes a chamber, a rotatable substrate holder inside the chamber, a nozzle above the rotatable substrate holder, a cover facing downward and fluidly coupled with the nozzle. The rotatable substrate holder is configured to mount one or more semiconductor wafers on the rotatable substrate holder. The nozzle is configured to spray a cleaning medium onto the one or more semiconductor wafers. The cover is of a shape having a top edge with a top cross-sectional area and a bottom edge with a bottom cross-sectional area. | 06-19-2014 |
| 20140202383 | WAFER PROCESSING SYSTEM USING MULTI-ZONE CHUCK - A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer. The process chamber is configured to perform a treatment on a front side of the wafer. The front side is opposite the back side. The process chamber includes therein a multi-zone chuck. The multi-zone chuck is configured to support the back side of the wafer. The multi-zone chuck has a plurality of zones with controllable clamping forces for securing the wafer to the multi-zone chuck. The controller is coupled to the metrology chamber and the multi-zone chuck. The controller is configured to control the clamping forces in the corresponding zones in accordance with measured values of the thickness of the first layer in the corresponding zones. | 07-24-2014 |
| 20140210506 | In-Situ Charging Neutralization - Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided. | 07-31-2014 |
| 20140220863 | HIGH THROUGHPUT CMP PLATFORM - A chemical-mechanical polishing system has a first polishing apparatus configured to perform a first chemical-mechanical polish on a workpiece and a second polishing apparatus configured to perform a second chemical-mechanical polish on the workpiece. A rework polishing apparatus comprising a rework platen and a rework CMP head is configured to perform an auxiliary chemical-mechanical polish on the workpiece when the workpiece is positioned on the rework platen. A measurement apparatus measures one or more parameters of the workpiece, and a transport apparatus transports the workpiece between the first polishing apparatus, second polishing apparatus, rework polishing apparatus, and measurement apparatus. A controller determines a selective transport of the workpiece to the rework polishing apparatus by the transport apparatus only when the one or more parameters are unsatisfactory. | 08-07-2014 |
| 20140235071 | SUBSTRATE RAPID THERMAL HEATING SYSTEM AND METHODS - A method and apparatus for rapid thermal heat treatment of semiconductor and other substrates is provided. A number of heat lamps arranged in an array or other configuration produce light and heat radiation. The light and heat radiation is directed through a heat slot that forms a radiation beam of high intensity light and heat. The radiation beam is directed to a platen that includes multiple substrates. The apparatus and method include a controller that controls rotational and translational motion of the platen relative to the heat slot and also controls the power individually and collectively supplied to the heat lamps. A program is executed which maneuvers the platen such that all portions of all substrates receive the desired thermal treatment, i.e. attain a desired temperature for a desired time period. | 08-21-2014 |
| 20140238864 | Layer by Layer Electro Chemical Plating (ECP) Process - The present disclosure relates to an electro-chemical plating (ECP) process that provides for an isotropic deposition, and a related apparatus. In some embodiments, the disclosed ECP process is performed by providing a substrate into an electroplating solution comprising a plurality of ions of a material to be deposited. A periodic patterned signal, which alternates between a first value and a different second value, is applied to the substrate. When the periodic patterned signal is at the first value, ions from the electroplating solution affix to the substrate. When the periodic patterned signal is at the second value, ions from the electroplating solution do not affix to the substrate. By using the periodic patterned signal to perform electro-chemical plating, the deposition rate of the plating process is reduced, resulting in an isotropic deposition over the substrate that mitigates gap fill problems (e.g., void formation). | 08-28-2014 |
| 20140273302 | Fine Temperature Controllable Wafer Heating System - Disclosed are a method and a system for processing wafers in fabricating a semiconductor device where disposing chemicals and wafer heating are needed for chemical reaction. A wafer is placed above a wafer heater such that a second surface faces the wafer heater, and heated from the second surface. A chemical layer is formed on an opposing first surface. The wafer heater is sized and configured to be capable of heating the entire second surface, and adapted to produce a locally differential temperature profile if needed. During heating, an actual temperature profile on the wafer may be monitored and transmitted to a computing system, which may generate a target temperature profile and control the wafer heater to adjust local temperatures on the wafer according to the target temperature profile. A supplemental heater for heating the chemicals may be used for finer control of the wafer temperature. | 09-18-2014 |
| 20140273420 | ION IMPLANTATION - One or more techniques or systems for ion implantation are provided herein. A pressure control module is configured to maintain a substantially constant pressure within an ion implantation or process chamber. Pressure is maintained based on an attribute of an implant layer, pressure data, feedback, photo resist (PR) outgassing, a PR coating rate, a space charge effect associated with the implant layer, etc. By maintaining pressure within the process chamber, effects associated with PR outgassing are mitigated, thereby mitigating neutralization of ions. By maintaining charged ions, better control over implantation of the ions is achieved, thus allowing ions to be implanted at a desired depth. | 09-18-2014 |
| 20150068559 | Device Manufacturing Cleaning Process Using Vaporized Solvent - A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The solvent-containing vapor is conducted to a substrate having debris or contaminants to clean the substrate, wherein the solvent-containing vapor condenses to form a liquid on a surface of the substrate. The liquid phase of the solvent-containing vapor is changed to a solid phase. The solid phase of the solvent-containing vapor is changed back to a liquid phase. The substrate is spun dried to remove the solvent-containing vapor in liquid phase and any debris or contaminants. | 03-12-2015 |
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| 20090053891 | Method for fabricating a semiconductor device - A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via hole is formed through the composite layer, wherein the via hole exposes a surface of the conductive layer. A protection layer is formed on a sidewall of the via hole so as to prevent out-gassing from the spin-on-glass layer. A barrier layer is formed on the protection layer and the conductive layer within the via hole. And a metal layer is deposited on the barrier layer within the via hole to fill the via hole. | 02-26-2009 |
| 20090236665 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 09-24-2009 |
| 20090236681 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 09-24-2009 |
| 20100181639 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices. | 07-22-2010 |
| 20110062500 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 03-17-2011 |
| 20110117709 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively. | 05-19-2011 |
| 20120056295 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 03-08-2012 |
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| 20110121426 | ELECTRONIC DEVICE WITH FUSE STRUCTURE AND METHOD FOR REPAIRING THE SAME - According to an embodiment of the invention, an electronic device with a fuse structure is provided. The electronic device includes a substrate, at least a conducting layer formed in or on the substrate and having a fuse area, and at least a lens disposed overlying the fuse area of the conducting layer, wherein the lens is substantially aligned with the fuse area and there is no optical device disposed between the lens and the fuse area. | 05-26-2011 |
| 20110311919 | METHOD FOR FABRICATING AN IMAGE SENSOR DEVICE - A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights. | 12-22-2011 |
| 20140264630 | Integrated Structure - An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate. | 09-18-2014 |
| 20140264869 | Semiconductor Device - A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via. | 09-18-2014 |
| 20140264912 | Semiconductor Device - A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure. | 09-18-2014 |
| 20140264913 | Semiconductor Device - A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect. | 09-18-2014 |
| 20140264915 | Stacked Integrated Circuit System - A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second chip to electrically connect the first chip and the second chip, wherein the memory cells of the first chip and the logic circuitries of the second chip are designed to be used collectively in order to perform complete memory functions, and wherein the first average pattern density is higher than the second average pattern density. | 09-18-2014 |
| 20140264917 | A Semiconductor Device with a Through-Silicon Via and a Method for Making the Same - A semiconductor device with a through-silicon via comprises a substrate with a front side and a backside and a through-silicon via penetrating the substrate with a circular shape on the front side and a corner-rounded rectangular shape on the back side. | 09-18-2014 |
| 20140264918 | Integrated Circuit Layout - An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV. | 09-18-2014 |
| 20140266418 | Stacked Chip System - A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other. | 09-18-2014 |
| 20140273435 | METHOD FOR FABRICATING A THROUGH-SILICON VIA - A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 μm and a depth of at least 5 μm. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value. | 09-18-2014 |
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| 20120120053 | APPARATUS AND METHODS FOR PROCESSING DIGITAL 3D OBJECTS - A digital 3D object processing apparatus is provided, for processing a digital 3D object comprising a plurality of sub-objects belonging to one of a plurality of digital 3D object formats, comprising: a communication unit coupled to a first outer computer through a network; an interface unit coupled to the communication unit, receiving an instruction from the first outer computer; and a control command unit coupled to the communication unit, transmitting a control command to the first outer computer, wherein the first outer computer establishes a relative position of the plurality of sub-objects according to the control command, and transmits the relative position and the plurality of sub-objects to the communication unit. | 05-17-2012 |
| 20130271352 | INTERACTIVE SYSTEM AND METHOD FOR OPERATING A PLURALITY OF FLEXIBLE DISPLAYS TO IMPLEMENT INTERACTIVE OPERATION - A method for operating a plurality of flexible displays to implement an interactive operation among the plurality of flexible displays is provided. The method is used between the plurality of flexible displays and a system control platform. Each flexible display is configured with a plurality of light sensors and a plurality of sensors and a processor. The method includes: quantifying, by each light sensor, a external luminosity value received by each flexible display; quantifying, by each sensor, a sensor-measuring value received by each flexible display; generating and transmitting, by the processor coupled to the light sensors and the sensors, luminosity information and sensor information according to the external luminosity values and the sensor-measuring values; and receiving, by the information platform, the luminosity information and the sensor information, and implements the interactive operation among the plurality of flexible displays between the plurality of flexible displays according to the sensor information. | 10-17-2013 |
| 20140059060 | SYSTEMS AND METHODS FOR PRESENTING POINT OF INTEREST (POI) INFORMATION IN AN ELECTRONIC MAP, AND STORAGE MEDIUM - A map system for presenting Point of Interest (POI) information is provided with an interface module, a storage unit, and a processing module. The interface module is coupled to a display device and provides an operation interface for receiving a search query and a condition of time period. The storage unit stores a plurality of POIs data and verified data of the POIs each corresponding to a respective one of different time periods. The processing module filters the POIs and the verified data according to the search query and the condition of time period to generate an electronic map, and displays the electronic map to present the filtered POIs via the interface module and the display device. | 02-27-2014 |
| 20140136618 | METHOD, DEVICE AND RECORDING MEDIA FOR SEARCHING TARGET CLIENTS - A method for searching target clients, applied to a mobile device coupled to a network, is provided. A target position and a target time are generated by a positioning unit and a time generating unit of the mobile device, respectively. A target clients search message is generated according to keywords input into the mobile device, the target position and the target time and then transmitted to a server coupled to the network through the network. Then a search result transmitted by the server through the network is received. The search result comprises at least one of a target clients amount, a target clients density and a target clients occurrence probability, which are retrieved from at least one social networks data and corresponding to the keywords, the target location and the target time. A map combined with the search result is displayed. | 05-15-2014 |
| 20140136911 | REMOTE MONITORING SYSTEMS AND RELATED METHODS AND RECORDING MEDIUMS USING THE SAME - Remote monitoring systems for remotely monitoring execution status of a PLC (Programmable Logic controller) program of a machine include a storage module, a parameter retrieval module and a monitoring module. The storage module stores ladder diagram information corresponding to a PLC source program, wherein the ladder diagram information includes PLC signal address relation information, a plurality of logic switches and a responsive collect command of each logic switch of a ladder diagram. The PLC signal address relation information indicates the relations of the logic switches on the ladder diagram. The parameter retrieval module respectively retrieves parameter data corresponding to the logic switches using the responsive collect commands. The monitoring module generates a status of ladder diagram according to the logic switches, the parameter data and the PLC signal address relation information to display the parameter data corresponding to each logic switch when the machine is executing the PLC source program. | 05-15-2014 |
| 20140143654 | SYSTEMS AND METHODS FOR GENERATING MOBILE APP PAGE TEMPLATE, AND STORAGE MEDIUM THEREOF - A system for generating a mobile APP page template is provided with an interface module, a processing module, and a storage module. The interface module receives at least one mobile APP page. The processing module is coupled to the interface module, and retrieves page components and mobile-device sensor information for activating at least one of the page components from the mobile APP page, and classifies the page components into categories and keeps a respective usage count and at least one attribute for each of the page components. Also, the processing module generates at least one mobile APP page template according to the categories, the usage counts, the attributes, and the mobile-device sensor information of the page components. Particularly, the mobile APP page template comprises the mobile-device sensor information and at least one template component activated by the mobile-device sensor information. | 05-22-2014 |
| 20140157147 | FEEDBACK SYSTEM, FEEDBACK METHOD AND RECORDING MEDIA THEREOF - The present invention discloses a feedback system. The feedback system includes an application executing module, a trigger module and a feedback interface module. The application executing module executes an application to display a plurality of display elements, wherein at least one of the display elements corresponds to at least one of a plurality of motion events provided for users to operate. The trigger module receives a first selection signal when the application executing module executes the application, wherein the first selection signal corresponds to an indicated feedback element, and the indicated feedback element is one of the display elements. The feedback interface module receives a first feedback content corresponding to the indicated feedback element and generates a first feedback message, when the trigger module receives the first selection signal, wherein the first feedback message includes the first feedback content and the first selection signal. | 06-05-2014 |
| 20140163856 | SENSING SYSTEM, SENSING METHOD, AND RECORDING MEDIUM THEREOF - A sensing system, a sensing method, and a recording medium thereof are provided, which are applicable to a sensing area formed of at least four boundary lines, in which neighboring boundary lines are at a straight angle, and each boundary line is at least three sensing points are set thereupon. Each sensing point implies a coordinate on XY plane. Each sensor provides a sensed value, location information and coordinate corresponding to a sensing point. The processor gets sensed values corresponding to all sensing points from the sensors, and estimates the estimated values of a plurality of expected estimated boundary points on each boundary line according to one of a plurality of estimation formulas and the sensed values of the three sensing points on each boundary line, in which the distance between each expected estimated boundary point and its other neighboring expected estimated boundary points is within a preset value. | 06-12-2014 |
| 20140164912 | GENERATING SYSTEM, METHOD OF INTERACTIVE PAGE TEMPLATES AND STORAGE MEDIUM THEREOF - A method for generating at least one interactive page template is provided. The at least one interactive page template includes at least one interactive component. The interactive component is a material which can be operated by at least one input signals of the mobile device and be presented by at least one output signals of a mobile device. The method includes: receiving, via a user interface, a setting command, wherein the setting command includes at least one material type and the input signals and output signals; obtaining, by a page component exploring module, at least one interactive page component from a page component repository according to the setting command; generating, by a template generating module, at least one interactive page template, wherein the interactive page template contains the interactive page component, according to the template integrating principle stored in a template integrating principle storage module; and displaying, by the user interface, the at least one interactive page template. | 06-12-2014 |
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| 20110159316 | MAGNETORESISTIVE DEVICE WITH PERPENDICULAR MAGNETIZATION - A magnetoresistive device with perpendicular magnetization includes a magnetic reference layer, a first magnetic multi-layer film, a tunneling barrier layer, a second magnetic multi-layer film, and a magnetic free layer. The magnetic reference layer has a first magnetization direction, perpendicular to the magnetic reference layer. The first magnetic multi-layer film, having non-magnetic material layer, is disposed in contact on the magnetic reference layer. The tunneling barrier layer is disposed in contact on the first magnetic multi-layer film. The second magnetic multi-layer film, having non-magnetic material layer, is disposed in contact on the tunneling barrier layer. The magnetic free layer is disposed in contact on the second magnetic multi-layer film, having a second magnetization direction capable of being switched to be parallel or anti-parallel to the first magnetization direction. | 06-30-2011 |
| 20130087757 | RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a resistive memory device is provided. A bottom electrode and a cup-shaped electrode connected to the bottom electrode are formed in an insulating layer. A cover layer extends along a first direction is formed and covers a first area surrounded by the cup-shaped electrode and exposes a second area and a third area surrounded by the cup-shaped electrode. A sacrificial layer is formed above the insulating layer. A stacked layer extends along a second direction and covers the second area surrounded by the cup-shaped electrode and a portion of the corresponding cover layer is formed. A conductive spacer material layer is formed on the stacked layer and the sacrificial layer. By using the sacrificial layer as an etch stop layer, the conductive spacer material layer is etched to form a conductive spacer at the sidewall of the stacked layer. | 04-11-2013 |
| 20130207209 | TOP-PINNED MAGNETIC TUNNEL JUNCTION DEVICE WITH PERPENDICULAR MAGNETIZATION - A top-pinned magnetic tunnel junction device with perpendicular magnetization, including a bottom electrode, a non-ferromagnetic spacer, a free layer, a tunneling barrier, a synthetic antiferromagnetic reference layer and a top electrode, is provided. The non-ferromagnetic spacer is located on the bottom electrode. The free layer is located on the non-ferromagnetic spacer. The tunnel insulator is located on the free layer. The synthetic antiferromagnetic reference layer is located on the tunneling barrier. The synthetic antiferromagnetic reference layer includes a top reference layer located on the tunneling barrier, a middle reference layer located on the bottom reference layer and a bottom reference layer located on the tunneling barrier. The magnetization of the top reference layer is larger than that of the bottom reference layer. The top electrode is located on the synthetic antiferromagnetic reference layer. | 08-15-2013 |
| 20140001586 | PERPENDICULARLY MAGNETIZED MAGNETIC TUNNEL JUNCTION DEVICE | 01-02-2014 |
| 20140361391 | MAGNETIC TUNNEL JUNCTION DEVICE WITH PERPENDICULAR MAGNETIZATION AND METHOD OF FABRICATING THE SAME - A magnetic tunnel junction device with perpendicular magnetization including a reference layer, a tunneling dielectric layer, a free layer and a capping layer is provided. The tunneling dielectric layer covers on the reference layer. The free layer covers on the tunneling dielectric layer. The capping layer is consisted of magnesium, aluminum and oxygen, and disposed on the free layer. | 12-11-2014 |
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| 20120169368 | TEST CIRCUIT OF SOURCE DRIVER - A test circuit of a source driver is disclosed. The test circuit includes a voltage selector and at least one digital-to-analog converter (DAC). The voltage selector has a plurality of first output terminals. The voltage selector outputs a first voltage at one of the first output terminals in a sequential order according to a selection signal and outputs a second voltage at the other first output terminals. Each of the at least one DACs has a plurality of the input terminals respectively coupled to the first output terminals and also has a second output terminal. The DAC transmits the first voltage received by one of the input terminals to the second output terminal in a sequential order according to the selection signal. | 07-05-2012 |
| 20120274493 | Digital-to-Analog Converter circuit with Rapid Built-in Self-test and Test Method - A digital-to-analog converter circuit with rapid built-in self-test is disclosed. The digital-to-analog converter includes a control unit for generating a selection control signal and a digital data control signal, a voltage switching module including a voltage switching module for receiving a first test voltage, a second testing end for receiving a second test voltage, and a plurality of switches, which is utilized for respectively arranging each switch to connect to the first testing end or the second testing end to output the corresponding switching selection signal, and a digital-to-analog converter for selecting an output testing voltage signal from the plurality of switching selection signals according to the digital data control signal. | 11-01-2012 |
| 20130266030 | Device and Method for Transmitting and Receiving Data - A data transmission device includes a data division unit for receiving an original transmission data and dividing the original transmission data into a plurality of division data; a data generation unit for generating a plurality of packet data according to the plurality of division data and a plurality of clock data, wherein each of the clock data is a multi-bit data; and a data output unit for outputting the plurality of packet data to a data reception device; where each of the packet data includes a division data and a clock data, each of the packet data corresponds to a packet data period, and the division data corresponds to a division data period of the packet data period and the clock data corresponds to a clock period of the packet data period. | 10-10-2013 |
| 20140049524 | METHOD FOR DISPLAYING ERROR RATES OF DATA CHANNELS OF DISPLAY - A method for displaying error rates of data channels of a display is provided. A timing controller of the display repeatedly transmits a test signal with a specific format to a first and a second source drivers of the display via a first and a second data channels of the display. During testing, a first number and a second number of times of the first source driver and the second source driver determining that the received test signal does not have the specific format are counted respectively. The first and the second source drivers control displaying of a first area and a second area of a panel of the display respectively according to the counted first and second numbers of times. Accordingly, the error rates of the data channels are presented on the panel of the display in a way that the error rates could be recognized more easily. | 02-20-2014 |
| 20140071106 | SOURCE DRIVER AND METHOD FOR UPDATING A GAMMA CURVE - A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data from the timing controller via a data bus, converts the first pixel data to a first drive voltage according to a first reference voltage group, and drives a display panel by the first drive voltage. The voltage controller receives a voltage command from the timing controller, generates and changes a first reference voltage configuration data according to the voltage command. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data to generate and adjust the first reference voltage group for applying to the first drive channel circuit. Furthermore, a method for updating a new gamma curve by the source driver is also provided. | 03-13-2014 |
| 20140078133 | PANEL DISPLAY APPARATUS - A panel display apparatus is provided which includes a timing controller, a plurality of source drivers, a first data path, and a second data path. The first data path and the second data path are both coupled between the timing controller and the source drivers. The timing controller transmits multiple display data to the source drivers via the first data path. When the source drivers detect an event (e.g. error event), the source drivers transmit at least one event data (e.g. notification data) to the timing controller via the second data path to notify the timing controller that event correction (e.g. error correction) is needed. | 03-20-2014 |
| 20140111494 | Self-detection Charge Sharing Module - A self-detection charge sharing module for a liquid crystal display device is disclosed. The self-detection charge sharing module includes at least one detecting unit, for detecting a plurality of input voltages of a plurality of operational amplifiers driving a plurality of data line sand a plurality of output voltage of the plurality of data line, to generate at least one detecting result, and at least one charge sharing unit, for conducting connection between at least one first data line and at least one second data line among the plurality of data line when the at least one detecting result indicates at least one corresponding first input voltage and at least one corresponding second input voltage among the plurality of input voltage have opposite voltage variation direction and vary toward each other. The at least one first input voltage and the at least one second input voltage maintain respective polarities. | 04-24-2014 |
| 20140132575 | TIMING CONTROLLER, SOURCE DRIVER, DISPLAY DRIVING CIRCUIT, AND DISPLAY DRIVING METHOD - A timing controller is provided. The timing controller includes a timing control circuit, a first scrambler and a second scrambler. The timing control circuit provides first source driving data and second source driving data. The first scrambler scrambles the first source driving data according to a first random number to generate first scrambled data. The second scrambler scrambles the second driving source data according to a second random number to generate second scrambled data. The second random number is different from the first random number. | 05-15-2014 |
| 20140132587 | Integrated Source Driver and Liquid Crystal Display Device Using the Same - The present invention discloses an integrated source driver for a liquid crystal display device. The integrated source driver includes a reference voltage generating circuit, for providing a plurality of adjustable voltage ranges within a supply voltage and a ground level, and a reference voltage selecting circuit, including a plurality of digital to analog converters, for selecting and generating a plurality of internal reference voltages from the plurality of adjustable voltage ranges, respectively. The plurality of adjustable voltage ranges decrease progressively. | 05-15-2014 |
| 20140160104 | DISPLAY DRIVING METHOD AND ASSOCIATED DRIVING CIRCUIT FOR DISPLAY APPARATUS - A display driving method and an associated driving circuit are provided, where the display driving method includes: checking relationships between two voltage levels respectively represented by two continuously received digital codes received by a specific digital code input terminal and a first predetermined threshold, and preferably further checking a relationship between at least one voltage level represented by at least one digital code of the two continuously received digital codes and a first predetermined zone, in order to determine whether to pre-charge a specific set of display cells within a plurality of sets of display cells, the specific set corresponding to the specific digital code input terminal; when it is determined to pre-charge the specific set of display cells, temporarily conducting a pre-charging voltage generator to the specific set of display cells to pre-charge the specific set of display cells. | 06-12-2014 |
| 20140160183 | TIMING SCRAMBLING METHOD AND TIMING CONTROL CIRCUIT THEREOF - A timing scrambling method, for a timing control device corresponding to a plurality of source driving devices, includes adjusting a selecting signal according to a clock signal; selecting one of a plurality of scrambling generating units according to the selecting signal to generate a timing scrambling signal; and generating scrambling data for the plurality of source driving devices according to the timing scrambling signal. | 06-12-2014 |
| 20140198021 | DISPLAY DRIVING APPARATUS - A display driving apparatus, including an image processor, a timing controller, and a plurality of source drivers, is provided. The image processor determines whether an image frame corresponding to a frame data is a static image and outputs the frame data and a determination result. The timing controller receives the frame data from the image processor and outputs the frame data. The source drivers receive the frame data from the timing controller and drive a display panel according to the frame data. Each of the source drivers includes a memory module configured to store the frame data corresponding to the static image. When the source drivers drive the display panel according to the frame data corresponding to the static image, the image processor stops outputting the frame data to the timing controller, and the timing controller stops outputting the frame data to the source drivers. | 07-17-2014 |
| 20140241459 | CLOCK-EMBEDDED DATA GENERATING APPARATUS AND TRANSMISSION METHOD THEREOF - A clock-embedded data generating apparatus and transmission method are disclosed. The steps of the transmission method include: generating a plurality of preamble signals according to a number sequence, where each of the preamble signals has a plurality of bits. The number sequence includes a plurality of values, and the bits of each of the preamble signals are decided by each of the corresponding values; transmitting the preamble signals during a plurality of preamble signal transmitting periods respectively, and transmitting a plurality of data signal during a plurality of data signal transmitting periods respectively. | 08-28-2014 |
| 20140320474 | DISPLAY DRIVER AND DISPLAY DIVING METHOD - A display driver, which comprises: a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising at least one first predetermined voltage level; a first image data providing apparatus, for outputting a first image data; and a detection controlling circuit, for determining if an output terminal of the first image data providing apparatus is pre-charged to the first predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level. | 10-30-2014 |
| 20140368553 | SOURCE DRIVER APPARATUS AND DRIVING METHOD OF DISPLAY PANEL - A source driver apparatus configured to drive a display panel is provided. The source driver apparatus includes a data operation circuit and a pixel driving circuit. The data operation circuit is configured to receive pixel data and perform a polarity determination operation on the pixel data to determine a polarity distribution information of pixels on the display panel. The pixel driving circuit is coupled to the data operation circuit. The pixel driving circuit is configured to drive the display panel according to the pixel data and the polarity distribution information. Furthermore, a driving method of the display panel is also provided. | 12-18-2014 |
| 20150042395 | SOURCE DRIVER AND METHOD TO REDUCE PEAK CURRENT THEREIN - A source driver and a method to reduce peak current of the source driver are provided. The source driver includes a latch circuit, a level shifter and a digital-to-analog converter (DAC) circuit. The latch circuit latches current bit-data. The latch circuit is coupled to an input terminal of the level shifter. The DAC circuit is coupled to an output terminal of the level shifter. When the current bit-data is not a complement of previous bit-data, the latch circuit selects and outputs the current bit-data to the input terminal of the level shifter, and the DAC circuit outputs a voltage corresponding to the output data of the level shifter. When the current bit-data is the complement of the previous bit-data, the latch circuit selects and outputs the previous bit-data to the input terminal of the level shifter, and the DAC circuit outputs a voltage corresponding to the current bit-data. | 02-12-2015 |
| 20150084947 | SOURCE DRIVER AND METHOD FOR DRIVING DISPLAY DEVICE - A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data and a first reference voltage group, for driving the display device. The voltage controller receives a voltage command during a line data transmitting period, a horizontal blanking period or a vertical blanking period for generating a first reference voltage configuration data. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data for applying the first reference voltage group to the first drive channel circuit. Furthermore, a method for driving a display device is also provided. | 03-26-2015 |
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| 20100328442 | HUMAN FACE DETECTION AND TRACKING DEVICE - A human face detection device includes a photosensitive element, a human face detection unit, and a skin color threshold generation unit. The photosensitive element is used for capturing a first image containing a first human face block. The human face detection unit compares the first image with at least one human face feature, so as to detect the first human face block. The skin color threshold generation unit is used for updating a skin color threshold value according to the detected first human face block. The skin color threshold value is used for filtering the first image signal to obtain a candidate region, the human face detection unit compares the candidate region with the at least one human face feature to obtain the first human face block, and the skin color threshold value determines whether the first human face block detected by the human face detection unit is correct. | 12-30-2010 |
| 20100328498 | SHOOTING PARAMETER ADJUSTMENT METHOD FOR FACE DETECTION AND IMAGE CAPTURING DEVICE FOR FACE DETECTION - A shooting parameter adjustment method for face detection includes (A) acquiring an image; (B) dividing the image into a plurality of blocks, and calculating a brightness value of each of the blocks; (C) selecting at least one of the plurality of blocks, and adjusting a shooting parameter according to the brightness value of the selected block; and (D) acquiring another image according to the shooting parameter, and performing a face detection procedure with the another image. The shooting parameter adjustment method can automatically adjust a shooting parameter of an image capturing device according to brightness of different blocks in an image. Therefore, by using this method, the brightness of a face, no matter being too high or too low, can be adjusted to a value suitable for face detection, so as to improve the accuracy of the face detection procedure. | 12-30-2010 |
| 20100329518 | DYNAMIC IMAGE COMPRESSION METHOD FOR HUMAN FACE DETECTION - A dynamic image compression method for human face detection includes the following steps. An original image is acquired. The image is divided into a plurality of blocks. A first brightness and a plurality of gradient values of each block are calculated. A second brightness of each block is calculated according to a brightness transformation function and the first brightness. A reconstruction image is generated according to the second brightness and the plurality of gradient values of each block. Human face detection is performed according to the reconstruction image. Therefore, gradient values within an original square are. When the human face detection process is performed through gradient direction information, a success rate of detection is greatly increased. | 12-30-2010 |
| 20120212639 | Image Sensor - An image sensor includes a sensor matrix including a plurality of sensing elements and a plurality of shutter control lines. Each sensing element includes an electronic shutter and a photo-detector, wherein the electronic shutter controls the exposure time of the photo-detector. Each shutter control line couples to a row or column of the electronic shutters, whereby different rows or columns of the electronic shutters can be independently controlled, and the photo-detectors in the same row or column can have the same exposure time. | 08-23-2012 |
| 20130106786 | Handwriting System and Sensing Method Thereof | 05-02-2013 |
| 20130155285 | Interactive Electronic Device - An interactive electronic device includes an image capture module, a response module and a processing module. The image capture module is configured to capture an image. The response module is configured to output a control signal according to a pattern contained in the image. The processing module is electrically connected to the image capture module and the response module and configured to drive the interactive electronic device according to the control signal. | 06-20-2013 |
| 20130162592 | Handwriting Systems and Operation Methods Thereof - A handwriting system includes a light source module, an image sensing apparatus and a processing circuit. The light source module is configured to provide a light source to illuminate an object on a plane. The image sensing apparatus is disposed on the plane and configured to capture an image of the object reflecting the light source. The processing circuit is electrically connected to the image sensing apparatus and configured to receive the image captured by the image sensing apparatus, analyze the shape of each of light spot(s) in the captured image and filter out the light spot(s) not qualified to the shape of the object. Another handwriting system and two handwriting system operation methods are also provided. | 06-27-2013 |
| 20140079284 | ELECTRONIC SYSTEM - An electronic system comprises an image-sensing device and a processor coupled with the image-sensing device. The image-sensing device includes an image-sensing area configured to generate a picture. The picture includes a noisy region. The processor is configured to select a tracking region from the portion of the picture outside of the noisy region. The tracking region corresponds to an operative region of the image sensing area. | 03-20-2014 |
| 20140362249 | INTERACTIVE ELECTRONIC DEVICE - An interactive electronic device includes an image capture module, a response module and a processing module. The image capture module is for capturing images. The processing module is for generating a first or second command set according to the image and output a control signal. The response module is for driving the interactive electronic device to perform a first continuous reaction corresponding to a specific pattern contained in the image according to the first command set or drive the interactive electronic device to perform a second continuous reaction according to the second command set. The processing module is further for replacing, adding or deleting at least a command in the first command set in a random manner thereby obtaining the second command set. | 12-11-2014 |
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| 20110119648 | ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY - A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology. | 05-19-2011 |
| 20110197168 | DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed. | 08-11-2011 |
| 20130074018 | MULTI-PATTERNING METHOD - A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop. | 03-21-2013 |
| 20130132913 | RECOGNITION OF TEMPLATE PATTERNS WITH MASK INFORMATION - Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons. | 05-23-2013 |
| 20130254726 | MULTI-PATTERNING METHOD - A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks. | 09-26-2013 |
| 20140068528 | BALANCING MASK LOADING - Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy mask assignment is inserted in the mask layout. In some embodiments, a window is created such that dummies within the window receive dummy mask assignments. In some embodiments, a halo is created such that the area of the polygon is determined based on the halo. Additionally, in some examples, the window and halo are shifted around the mask layout. In this manner, balanced mask loading is provided, thus enhancing a yield associated with the mask layout, for example. | 03-06-2014 |
| 20140101623 | METHOD OF MERGING COLOR SETS OF LAYOUT - A method includes determining one or more potential merges corresponding to a color set A | 04-10-2014 |
| 20140151751 | DENSITY GRADIENT CELL ARRAY - One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions. | 06-05-2014 |
| 20140208282 | CONFLICT DETECTION FOR SELF-ALIGNED MULTIPLE PATTERNING COMPLIANCE - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict. | 07-24-2014 |
| 20140223391 | RECOGNITION OF TEMPLATE PATTERNS WITH MASK INFORMATION - Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons. | 08-07-2014 |
| 20140289684 | BALANCING MASK LOADING - Among other things, techniques for balancing mask loading are provided for herein. In some embodiments, one or more windows are defined within a layout. Based upon polygons comprised within respective windows, a localized mask loading is computed for the layout. In some embodiments, a global mask loading is also computed for the layout. Using the localized mask loading and the global mask loading, if computed, a loading effect of a plurality of mask pattern schemes is evaluated to identify a mask pattern scheme having a desired loading effect. | 09-25-2014 |
| 20140325464 | CONFLICT DETECTION FOR SELF-ALIGNED MULTIPLE PATTERNING COMPLIANCE - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict. | 10-30-2014 |
| 20140372958 | TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION - Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium. | 12-18-2014 |
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| 20090149570 | Plasticizer, a biodegradable material comprising the plasticizer and application thereof - The present invention relates to a Plasticizer, which is fabricated by mixing monomers of biodegradable polymer with bio-molecules subsequently to deal the mixture with thermal treatment. The Biodegradable material comprising the Plasticizer has high melt index which is contributive for the processing of thermal processing, and the microwave-tolerance and water-resistance of the material makes the material suitable for food packaging. | 06-11-2009 |
| 20100270238 | METHOD FOR TRANSFERRING INORGANIC OXIDE NANOPARTICLES FROM AQUEOUS PHASE TO ORGANIC PHASE - A method for transferring inorganic oxide nanoparticles from aqueous phase to organic phase. A modifier is used to change the surface polarity of inorganic oxide nanoparticles, followed by using proper solvents to transfer the modified inorganic oxide nanoparticles form aqueous phase to organic phase. The organic dispersion of modified inorganic oxide nanoparticles can be combined with a polymer to provide a polymer composite with the nanoparticles uniformly dispersed therein. | 10-28-2010 |
| 20120088852 | PLASTICIZER, A BIODEGRADABLE MATERIAL COMPRISING THE PLASTICIZER AND APPLICATION THEREOF - The present invention relates to a Plasticizer, which is fabricated by mixing monomers of biodegradable polymer with bio-molecules subsequently to deal the mixture with thermal treatment. The Biodegradable material comprising the Plasticizer has high melt index which is contributive for the processing of thermal processing, and the microwave-tolerance and water-resistance of the material makes the material suitable for food packaging. | 04-12-2012 |
| 20120112219 | Gradient Composite Material and Method of Manufacturing the Same - Method of manufacturing gradient composite material comprises steps of providing plural surface modified inorganic nanoparticles with functional groups or oligomers with functional groups; transferring the surface modified inorganic nanoparticles or oligomers with functional groups into an organic matrix to form a mixture; performing a photo polymerization step or a thermo-polymerization step for polymerizing and generating a gradient distribution of the surface modified inorganic nanoparticles or oligomers with functional groups in the mixture; and curing the mixture to solidify the organic matrix and form a structure with gradient composite, wherein the organic matrix is transferred into an organic polymer after curing. | 05-10-2012 |
| 20140094544 | PLASTICIZER, A BIODEGRADABLE MATERIAL COMPRISING THE PLASTICIZER AND APPLICATION THEREOF - The present embodiment relates to a Plasticizer, which is fabricated by mixing monomers of biodegradable polymer with bio-molecules subsequently to deal the mixture with thermal treatment. The Biodegradable material comprising the Plasticizer has high melt index which is contributive for the processing of thermal processing, and the microwave-tolerance and water-resistance of the material makes the material suitable for food packaging. | 04-03-2014 |
| 20140319047 | FILTRATION MATERIAL AND METHOD FOR FABRICATING THE SAME - The disclosure provides a filtration material and a method for fabricating the same. The filtration material includes a supporting layer, and a composite layer, wherein the composite layer includes an ionic polymer and an interfacial polymer. Particularly, the ionic polymer and the interfacial polymer are intertwined with each other, resulting from ionic bonds formed between the ionic polymer and the interfacial polymer. | 10-30-2014 |
| Patent application number | Description | Published |
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| 20090137947 | System and method of wireless physiological signal integration - A system of a wireless physiological signal integration is provided. The system includes a wireless transmission sensor chip and a drug delivering system, wherein the wireless transmission sensor chip includes a sensor sensing a physiological signal of a patient, a signal conversion module converting the physiological signal into a converted signal, and a wireless transmission module wirelessly transmitting the converted signal, and the drug delivering system determines a dose of a drug and a timing for providing the drug according to the converted signal. | 05-28-2009 |
| 20090272180 | CONTINUOUS TESTING DEVICE AND CONTINUOUS TESTING SYSTEM - A continuous testing device for testing the concentration of a target object in a fluid is provided. The continuous testing device includes a first chip, a signal source and a second chip. The first chip includes a separating unit and a reacting unit. The separating unit separates the target object from a non-target object in the fluid. The reacting unit enables the fluid having separated out the non-target object to react with a reagent. The signal source provides a signal passing through the fluid having reacted with the reagent. The second chip disposed at one side of the first chip includes a signal transducing element and a processing unit. The signal transducing element receives the signal passing through the fluid and outputs an electronic signal corresponding to the input signal. The processing unit acquires the concentration of the target object according to the electronic signal. | 11-05-2009 |
| 20090273831 | LIGHT MODULE, OPTICAL TWEEZERS GENERATOR AND DARK FIELD MICROSCOPE - A light module is provided. The light module applied to a dark field microscope is used for illuminating an object. The light module includes a light beam, a reflection component and a condensing component. The light beam has several lights. The reflection component is used for converting the lights radiating along a beginning direction to a circular beam substantially radiating along the beginning direction. The circular beam passes through the condensing component and is focused on the object. A part of the circular beam passing through the condensing component is scattered by the object. | 11-05-2009 |
| 20110203354 | Continuous Testing Method - A continuous testing method for testing the concentration of a target object in a fluid is provided. The method comprises the following steps. A focused light is provided in the fluid to separate the target object from a non-target object in the fluid by changing the movement direction of the target object and the non-target object. The fluid having separated out the non-target object is enabled to react with a reagent. A signal is provided to pass through the fluid having reacted with the reagent. The signal passing through the fluid is received and an electronic signal is outputted corresponding to the input signal. The concentration of the target object is acquired according to the electronic signal. | 08-25-2011 |
| 20120043209 | MICROFLUIDIC CONTROL APPARATUS AND OPERATING METHOD THEREOF - A microfluidic control apparatus and operating method thereof. The microfluidic control apparatus includes a photoconductive material layer and a flow passage. When a light with a specific optical pattern is emitted toward the photoconductive material layer, at least three virtual electrodes are formed on the photoconductive material layer according to the specific optical pattern. The at least three virtual electrodes include a first virtual electrode, a second virtual electrode and a third virtual electrode disposed beside the first virtual electrode. There is a specific proportion among a distance between first virtual electrode and third virtual electrode, a width of first virtual electrode, a distance between first virtual electrode and second virtual electrode, and a width of second virtual electrode. When the specific optical pattern changes, the at least three virtual electrodes also change to generate an electro-osmotic force to control the moving state of a microfluid in a flow passage. | 02-23-2012 |
| 20130273610 | Method of Manufacturing Nanoparticle Chain - A method of manufacturing a nanoparticle chain is disclosed. The method comprises the steps of: providing a single-stranded circular primer with a determined length, and amplifying the single-stranded circular primer into single-stranded DNA nanotemplate by an isothermal nucleotide amplification reaction such that an end of the single-stranded DNA nanotemplate is fixed to a surface of a substrate; and adding a single-stranded DNA probe conjugated with nanoparticle at one end of which, and attaching the single-stranded DNA probe to the corresponding sequence on the single-stranded DNA nanotemplate to form a nanoparticles chain. The method of manufacturing a nanoparticle chain further comprises providing a fluid, and the flowing direction of the fluid controls the aligning direction of the nanoparticle chain. Wherein, the inter-nanoparticle distance of the nanoparticle chain can be adjusted by adjusting a reaction temperature or adding the single-stranded DNA probe without conjugating with nanoparticles. | 10-17-2013 |
| 20140034499 | MICROFLUIDIC CONTROL APPARATUS AND OPERATING METHOD THEREOF - A microfluidic control apparatus operating method is disclosed. The microfluidic control apparatus operating method is applied in a microfluidic control apparatus, and the microfluidic control apparatus includes a photoconductive material layer and a flow passage. The microfluidic control apparatus operating method includes steps of (a) when a light with a specific optical pattern is emitted toward the photoconductive material layer, at least three virtual electrodes being formed on the photoconductive material layer according to the specific optical pattern; (b) when the specific optical pattern changes, the at least three virtual electrodes also changing to generate an electro-osmotic force to control a moving state of a microfluid in the flow passage. | 02-06-2014 |
