Patent application number | Description | Published |
20130256875 | SEMICONDUCTOR PACKAGE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 10-03-2013 |
20140134797 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips. | 05-15-2014 |
20140183721 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved. | 07-03-2014 |
20140332976 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement. | 11-13-2014 |
20140342505 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant. | 11-20-2014 |
20140342506 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place. | 11-20-2014 |
20140342507 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 11-20-2014 |
20150294938 | CONDUCTIVE VIA STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias. | 10-15-2015 |