Patent application number | Description | Published |
20120124507 | ELECTRONIC BACKUP OF APPLICATIONS - Systems and methods are provided for storing and restoring digital data. In some implementations, a method is provided. The method includes receiving, while a current view of an application is displayed in a user interface, a first user input requesting that a history view associated with the current view of the application be displayed, retrieve data associated with the history view, determining a presentation format for the data, and displaying the history view in response to the first user input in accordance with the presentation format, the history view including data associated with at least a first visual representation of an earlier version of the current view of the application. | 05-17-2012 |
20120158854 | Message Focusing - A method and apparatus of a device that focuses messages is described. In an exemplary method, the device receives a first and second group of message. The device further selects a related message from the second group of messages that is related to each message in the first group. This selecting is based on an affinity group, where the affinity group includes a message address that occurs in at least one of the messages in the second group and the affinity group is determined using the message addresses contained in the first and second groups. | 06-21-2012 |
20120158856 | Message Focusing - A method and apparatus of a device that focuses messages is described. In an exemplary method, the device receives a first and second group of message. The device further selects a related message from the second group of messages that is related to each message in the first group. This selecting is based on an affinity group, where the affinity group includes a message address that occurs in at least one of the messages in the second group and the affinity group is determined using the message addresses contained in the first and second groups. | 06-21-2012 |
20120182316 | Assisted Image Selection - Assisted face selection is disclosed. According to some implementations, a method can include obtaining contact information associated with a contact and displaying on an interface of a computing device an image (e.g., a thumbnail image) representative of the contact. The method can include receiving an indication to change the contact-representative image, determining that one or more other images from a plurality of other images correspond to the contact based on the contact information, and displaying the one or more other images. The method can include receiving a selection of one of the one or more other images and displaying on the interface the selected image as the contact-representative image. Receiving the indication can include receiving a selection of the displayed contact-representative image. Automatic selection of images is also disclosed. | 07-19-2012 |
20130205251 | User Interface for Accessing Documents from a Computing Device - An application-centric model is employed for the storage, searching and retrieval of documents. By entering a command directed to a particular application program, such as clicking on an icon for that program, a user interface panel displays documents stored on the computing device that are associated with that application. From the panel, the user can perform various actions with respect to the displayed documents. | 08-08-2013 |
20130311597 | LOCALLY BACKED CLOUD-BASED STORAGE - A popular service offered by many cloud computing systems is cloud-based storage. To enhance this service, the cloud-based storage can be extended through the use of a local storage device. A local storage device, such as a network enabled external hard drive, can be made available via a user's Internet connection. The local storage device can then be used to transparently store the user's content. That is, the user can still back up their devices to the cloud, but in some cases instead of the content residing in the cloud-based storage, it can reside on the local storage device without additional action required by the user. When the user requests the content, the content can be retrieved from the local storage device and returned to the requesting client device without the client device knowing where the content was stored. | 11-21-2013 |
20130311598 | CLOUD-BASED DATA ITEM SHARING AND COLLABORATION AMONG GROUPS OF USERS - A cloud computing system can be used to facilitate data item sharing and collaboration among groups of users through the creation and management of collections. A group of users, each of which is associated with at least one client device, can subscribe to a collection. A subscribed user can create a data item locally on a client device and assign the data item to a collection. In response to the assignment, each user subscribed to the collection can receive and store a copy of the data item locally on a client device. Any modifications made to a local copy of the data item can automatically be distributed to each subscribed user's client device. The modifications, including conflicting modifications, can be merged into the local copy. | 11-21-2013 |
20130311986 | CLOUD-BASED APPLICATION RESOURCE FILES - A cloud computing system can be used to transparently reduce the storage space of an application on a client device. An application can be installed with a minimal set of application resource files. The remaining application resource files can be replaced with application resource file placeholders, which can have the appearance of application resource files but are in fact empty files. When an application requests an application resource file, an application resource file retrieval process installed on the client device can detect the difference between an application resource file and an application resource file placeholder. The application resource file retrieval process can trigger a fault in response to detecting an application resource file placeholder, which causes the client device to obtain the requested application resource file from a remote storage location, such as cloud-based storage. Additionally, installed application resource files can be replaced with application resource file placeholders. | 11-21-2013 |
20140059469 | Electronic Backup of Applications - Systems and methods are provided for storing and restoring digital data. In some implementations, a method is provided. The method includes receiving, while a current view of an application is displayed in a user interface, a first user input requesting that a history view associated with the current view of the application be displayed, retrieve data associated with the history view, determining a presentation format for the data, and displaying the history view in response to the first user input in accordance with the presentation format, the history view including data associated with at least a first visual representation of an earlier version of the current view of the application. | 02-27-2014 |
20140289287 | METHODS AND SYSTEMS FOR MANAGING DATA - Systems and methods for managing data, such as metadata. In one exemplary method, metadata from files created by several different software applications are captured, and the captured metadata is searched. The type of information in metadata for one type of file differs from the type of information in metadata for another type of file. Other methods are described and data processing systems and machine readable media are also described. | 09-25-2014 |
Patent application number | Description | Published |
20100122385 | METHOD AND APPARATUS OF OPERATING A SCANNING PROBE MICROSCOPE - An improved mode of AFM imaging (Peak Force Tapping (PFT) Mode) uses force as the feedback variable to reduce tip-sample interaction forces while maintaining scan speeds achievable by all existing AFM operating modes. Sample imaging and mechanical property mapping are achieved with improved resolution and high sample throughput, with the mode workable across varying environments, including gaseous, fluidic and vacuum. | 05-13-2010 |
20110167524 | METHOD AND APPARATUS OF OPERATING A SCANNING PROBE MICROSCOPE - An improved mode of AFM imaging (Peak Force Tapping (PFT) Mode) uses force as the feedback variable to reduce tip-sample interaction forces while maintaining scan speeds achievable by all existing AFM operating modes. Sample imaging and mechanical property mapping are achieved with improved resolution and high sample throughput, with the mode being workable across varying environments, including gaseous, fluidic and vacuum. Ease of use is facilitated by eliminating the need for an expert user to monitor imaging. | 07-07-2011 |
20120131702 | Method and Apparatus of Using Peak Force Tapping Mode to Measure Physical Properties of a Sample - An improved mode of AFM imaging (Peak Force Tapping (PFT) Mode) uses force as the feedback variable to reduce tip-sample interaction forces while maintaining scan speeds achievable by all existing AFM operating modes. Sample imaging and mechanical property mapping are achieved with improved resolution and high sample throughput, with the mode being workable across varying environments, including gaseous, fluidic and vacuum. Ease of use is facilitated by eliminating the need for an expert user to monitor imaging. | 05-24-2012 |
20130276174 | Method and Apparatus of Electrical Property Measurement Using an AFM Operating in Peak Force Tapping Mode - An apparatus and method of collecting topography, mechanical property data and electrical property data with an atomic force microscope (AFM) in either a single pass or a dual pass operation. PFT mode is preferably employed thus allowing the use of a wide range of probes, one benefit of which is to enhance the sensitivity of electrical property measurement. | 10-17-2013 |
20140223615 | Method and Apparatus of Operating a Scanning Probe Microscope - Methods and apparatuses are provided for automatically controlling and stabilizing aspects of a scanning probe microscope (SPM), such as an atomic force microscope (AFM), using Peak Force Tapping (PFT) Mode. In an embodiment, a controller automatically controls periodic motion of a probe relative to a sample in response to a substantially instantaneous force determined, and automatically controls a gain in a feedback loop. A gain control circuit automatically tunes a gain based on separation distances between a probe and a sample to facilitate stability. Accordingly, instability onset is quickly and accurately determined during scanning, thereby eliminating the need of expert user tuning of gains during operation. | 08-07-2014 |
20140283229 | Method and Apparatus of Operating a Scanning Probe Microscope - An improved mode of AFM imaging (Peak Force Tapping (PFT) Mode) uses force as the feedback variable to reduce tip-sample interaction forces while maintaining scan speeds achievable by all existing AFM operating modes. Sample imaging and mechanical property mapping are achieved with improved resolution and high sample throughput, with the mode workable across varying environments, including gaseous, fluidic and vacuum. | 09-18-2014 |
Patent application number | Description | Published |
20100092697 | SCALABLE, HIGH-THROUGHPUT, MULTI-CHAMBER EPITAXIAL REACTOR FOR SILICON DEPOSITION - One embodiment provides an apparatus for material deposition. The apparatus includes a reaction chamber, and a pair of susceptors. Each susceptor has a front side and a back side, and the front side mounts substrates. The susceptors are positioned vertically in such a way that the front sides of the susceptors face each other, and the vertical edges of the susceptors are in contact with each other, thereby forming a substantially enclosed narrow channel between the substrates. The apparatus also includes a number of gas nozzles for injecting reaction gases. The gas nozzles are controlled in such a way that gas flow directions inside the chamber can be alternated, thereby facilitating uniform material deposition. The apparatus includes a number of heating units situated outside the reaction chamber. The heating units are arranged in such a way that they radiate heat energy directly to the back sides of the susceptors. | 04-15-2010 |
20100092698 | SCALABLE, HIGH-THROUGHPUT, MULTI-CHAMBER EPITAXIAL REACTOR FOR SILICON DEPOSITION - One embodiment provides an apparatus for material deposition. The apparatus includes a reaction chamber, and a pair of susceptors. Each susceptor has a front side mounting substrates and a back side. The front sides of the vertically positioned susceptors face each other, and the vertical edges of the susceptors are in contact with each other. The apparatus also includes a number of gas nozzles for injecting reaction gases. The gas flow directions inside the chamber can be alternated by controlling the gas nozzles. The gas nozzles are configured to inject a small amount of purge gas including at least one of: HCl, SiCl | 04-15-2010 |
20110067632 | STACKABLE MULTI-PORT GAS NOZZLES - One embodiment provides a reactor for material deposition. The reactor includes a chamber and at least one gas nozzle. The chamber includes a pair of susceptors, each having a front side and a back side. The front side mounts a number of substrates. The susceptors are positioned vertically so that the front sides of the susceptors face each other, and the vertical edges of the susceptors are in contact with each other, thereby forming a substantially enclosed narrow channel between the substrates mounted on different susceptors. The gas nozzle includes a gas-inlet component situated in the center and a detachable gas-outlet component stacked around the gas-inlet component. The gas-inlet component includes at least one opening coupled to the chamber, and is configured to inject precursor gases into the chamber. The detachable gas-outlet component includes at least one opening coupled to the chamber, and is configured to output exhaust gases from the chamber. | 03-24-2011 |
20110277688 | DYNAMIC SUPPORT SYSTEM FOR QUARTZ PROCESS CHAMBER - One embodiment of the present invention provides a support system for providing dynamic support to a deposition reactor. The system includes a coupling mechanism configured to provide coupling between the deposition reactor and the support system, an attachment mechanism configured to attach the support system to an external frame, and at least one gas bellows situated between the coupling mechanism and the attachment mechanism. | 11-17-2011 |
20110277690 | MULTI-CHANNEL GAS-DELIVERY SYSTEM - One embodiment of the present invention provides a gas-delivery system for delivering reaction gas to a reactor chamber. The gas-delivery system includes a main gas-inlet port for receiving reaction gases and a gas-delivery plate that includes a plurality of gas channels. A gas channel includes a plurality of gas holes for allowing the reaction gases to enter the reactor chamber from the gas channel. The gas-delivery system further includes a plurality of sub-gas lines coupling together the main gas-inlet port and the gas-delivery plate, and a respective sub-gas line is configured to deliver a portion of the received reaction gases to a corresponding gas channel. | 11-17-2011 |
20110283941 | STABLE WAFER-CARRIER SYSTEM - One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor. | 11-24-2011 |
Patent application number | Description | Published |
20100241811 | Multiprocessor Cache Prefetch With Off-Chip Bandwidth Allocation - Technologies are generally described for allocating available prefetch bandwidth among processor cores in a multiprocessor computing system. The prefetch bandwidth associated with an off-chip memory interface of the multiprocessor may be determined, partitioned, and allocated across multiple processor cores. | 09-23-2010 |
20100274971 | Multi-Core Processor Cache Coherence For Reduced Off-Chip Traffic - Technologies are generally described herein for maintaining cache coherency within a multi-core processor. A first cache entry to be evicted from a first cache may be identified. The first cache entry may include a block of data and a first tag indicating an owned state. An owner eviction message for the first cache entry may be broadcasted from the first cache. A second cache entry in a second cache may be identified. The second cache entry may include the block of data and a second tag indicating a shared state. The broadcasted owner eviction message may be detected with the second cache. An ownership acceptance message for the second cache entry may be broadcasted from the second cache. The broadcasted ownership acceptance message may be detected with the first cache. The second tag in the second cache entry may be transformed from the shared state to the owned state. | 10-28-2010 |
20110153946 | DOMAIN BASED CACHE COHERENCE PROTOCOL - Briefly stated, technologies are generally described for accessing a data block in a cache with a domain based cache coherence protocol. A first processor in a first tile and first domain can be configured to evaluate a request to access the data block. A cache in a second tile in the first domain can be configured to send the data block to the first tile when the data block is cached in the second tile. The first processor can be configured to send the request to a third tile in another domain when the cached location is outside the first processor's domain. The third processor can be configured to determine and send the request to a data domain associated with the cached location of the data block. A fourth tile can be configured to receive the request and send the data block to the first tile. | 06-23-2011 |
20110161346 | DATA STORAGE AND ACCESS IN MULTI-CORE PROCESSOR ARCHITECTURES - Technologies are generally described for a system for sending a data block stored in a cache. In some examples described herein, a system may comprise a first processor in a first tile. The first processor is effective to generate a request for a data block, the request including a destination identifier identifying a destination tile for the data block, the destination tile being distinct from the first tile. Some example systems may further comprise a second tile effective to receive the request, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request to the data tile. Some example systems may still further comprise a data tile effective to receive the request from the second tile, the data tile effective to send the data block to the destination tile. | 06-30-2011 |
20120096239 | Low Power Execution of a Multithreaded Program - Technologies for low power execution of one or more threads of a multithreaded program by one or more processing elements are generally disclosed. | 04-19-2012 |
20120166735 | DATA STORAGE AND ACCESS IN MULTI-CORE PROCESSOR ARCHITECTURES - Technologies are generally described for a system for sending a data block stored in a cache. In some examples described herein, a system may comprise a first processor in a first tile. The first processor is effective to generate a request for a data block, the request including a destination identifier identifying a destination tile for the data block, the destination tile being distinct from the first tile. Some example systems may further comprise a second tile effective to receive the request, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request to the data tile. Some example systems may still further comprise a data tile effective to receive the request from the second tile, the data tile effective to send the data block to the destination tile. | 06-28-2012 |
20120173819 | Accelerating Cache State Transfer on a Directory-Based Multicore Architecture - Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile. | 07-05-2012 |
20120246446 | Dynamically Determining the Profitability of Direct Fetching in a Multicore Architecture - Technologies are generally described herein for determining a profitability of direct fetching in a multicore processor. The multicore processor may include a first and a second tile. The first tile may include a first core and a first cache. The second tile may include a second core, a second cache, and a fetch location pointer register (FLPR). The multicore processor may migrate a thread executing on the first core to the second core. The multicore processor may store a location of the first cache in the FLPR. The multicore processor may execute the thread on the second core. The multicore processor may identify a cache miss for a block in the second cache. The multicore processor may determine whether a profitability of direct fetching of the block indicates direct fetching or directory-based fetching. The multicore processor may perform direct fetching or directory-based fetching based on the determination. | 09-27-2012 |
20120317361 | STORAGE EFFICIENT SECTORED CACHE - Technologies are generally described for a system for copying particular data in a particular sector of a particular block from a memory into a cache, in some examples, the cache includes a tag array and a data array. In some examples, a processor may be adapted to copy data in the particular sector from the memory into a way of the data array starling at a start sector. In some examples, the processor may be adapted to update the tag array to identify the particular sector. In some examples, the processor may be adapted to update the tag array to identify the way in the data array, hi some examples, the processor may be adapted to update the tag array to identify the start sector. | 12-13-2012 |
20130054546 | HARDWARE-BASED ARRAY COMPRESSION - Technologies are generally described herein for compressing an array using hardware-based compression and performing various instructions on the compressed array. Some example technologies may receive an instruction adapted to access an address in an array. The technologies may determine whether address is compressible. If the address is compressible, then the technologies may determine a compressed address of a compressed array based on the address. The compressed array may represent a compressed layout of the array where a reduced size of each compressed element in the compressed array is smaller than an original size of each element in the array. The technologies may access the compressed array at the compressed address in accordance with the instruction. | 02-28-2013 |
20130191605 | MANAGING ADDRESSABLE MEMORY IN HETEROGENEOUS MULTICORE PROCESSORS - Technologies described herein generally describe technologies for managing addressable memories in a heterogeneous multicore chip. Technologies may be adapted to determine whether swapping a first data segment and a second data segment is suitable. The first data segment may be stored in a first addressable memory, and the second data segment may be stored in a second addressable memory. If the swapping is determined to be suitable, then the technologies may be adapted to swap the first data segment and the second data segment. As a result of the swap, the first data segment will be stored in the second addressable memory, and the second data segment will be stored in the first addressable memory. The technologies may also be adapted to update corresponding swap status indicators to indicate that the first data segment and the second data segment have moved. | 07-25-2013 |
20130205141 | Quality of Service Targets in Multicore Processors - Technologies are described herein for adapting a processor core on a multicore processor to achieve a quality of service target. Some example technologies may identify a target level of a resource on the computer. The technologies may identify a first utilization value and a second utilization value of the resource when the processor core operates at a first frequency and a second frequency. The technologies may generate a linear interpolation between a first point and a second point. Coordinates of the first point may include the first frequency and the first utilization value. Coordinates of the second point may include the second frequency and the second utilization value. The technologies may set the processor core to operate at a third frequency, which can be specified as one of the coordinates in an intersection point between the linear interpolation and the target level. | 08-08-2013 |
20130268943 | BALANCED PROCESSING USING HETEROGENEOUS CORES - Technologies are generally described for a multi-processor core and a method for transferring threads in a multi-processor core. In an example, a multi-core processor may include a first group including a first core and a second core. A first sum of the operating frequencies of the cores in the first group corresponds to a first total operating frequency. The multi-core processor may further include a second group including a third core. A second sum of the operating frequencies of the cores in the second group may correspond to a second total operating frequency that is substantially the same as the first total operating frequency. A hardware controller may be configured in communication with the first, second and third core. A memory may be configured in communication with the hardware controller and may include an indication of at least the first group and the second group. | 10-10-2013 |
20140026148 | LOW POWER EXECUTION OF A MULTITHREADED PROGRAM - Technologies for low power execution of one or more threads of a multithreaded program by one or more processing elements are generally disclosed. | 01-23-2014 |
Patent application number | Description | Published |
20130346714 | Hardware-Based Accelerator For Managing Copy-On-Write - Technologies are described herein for providing a hardware-based accelerator adapted to manage copy-on-write. Some example technologies may identify a read request adapted to read a block at an original memory address. The technologies may utilize the hardware-based accelerator to determine whether the block is located at the original memory address. When a determination is made that the block is located in at the original memory address, the technologies may utilize the hardware-based accelerator to pass the original memory address so that the read request can be performed utilizing the original memory address. When a determination is made that the block is not located in the memory at the original memory address, the technologies may utilize the hardware-based accelerator to generate a new memory address and to pass the new memory address so that the read request can be performed utilizing the new memory address. | 12-26-2013 |
20140040676 | DIRECTORY ERROR CORRECTION IN MULTI-CORE PROCESSOR ARCHITECTURES - Technologies are generally described that relate to processing cache coherence information and processing a request for a data block. In some examples, methods for processing cache coherence information are described that may include storing in a directory a tag identifier effective to identify a data block. The methods may further include storing a state identifier in association with the tag identifier. The state identifier may be effective to identify a coherence state of the data block. The methods may further include storing sharer information in association with the tag identifier. The sharer information may be effective to indicate one or more caches storing the data block. The methods may include storing, by the controller in the directory, replication information in association with the sharer information. The replication information may be effective to indicate a type of replication of the sharer information in the directory, and effective to indicate replicated segments. | 02-06-2014 |
20140059560 | RESOURCE ALLOCATION IN MULTI-CORE ARCHITECTURES - Technologies are generally described for a method, device and architecture effective to allocate resources. In an example, the method may include associating first and second resources with first and second resource identifiers and mapping the first and resource identifiers to first and second sets of addresses in a memory, respectively. The method may include identifying that the first resource is at least partially unavailable. The method may include mapping the second resource identifier to at least one address of the first set of addresses in the memory when the first resource is identified as at least partially unavailable. The method may include receiving a request for the first resource, wherein the request identifies a particular address of the addresses in the first set of addresses. The method may include analyzing the particular address to identify a particular resource and allocating the request to the particular resource. | 02-27-2014 |
20140082297 | CACHE COHERENCE DIRECTORY IN MULTI-PROCESSOR ARCHITECTURES - Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses. | 03-20-2014 |
20140119363 | Waved Time Multiplexing - Technologies generally described herein relate to waved time multiplexing. In some examples, a command flit can be transmitted from a sender node of a network-on-chip (“NOC”) to a destination node of the NOC via an intermediate node along a circuit-switched path. The command flit can include an interval period and a release duration. When the command flit has been transmitted, one or more data flits can be transmitted from the sender node to the destination node via the intermediate node along the circuit-switched path. The sender node, the destination node, and the intermediate node can be configured to reserve router resources of the sender node, the destination node, and the intermediate node respectively for circuit-switched traffic during a use duration of the interval period and to release the router resources for packet-switched traffic during the release duration in a waved time multiplex arrangement. | 05-01-2014 |
20140149674 | Performance and Energy Efficiency While Using Large Pages - Technologies are described herein for improving performance and energy efficiency in a computing system while using a large memory page size. Some example technologies may configure a main memory of the computing system to include a page-to-chunk table and a data area. The page-to-chunk table may include multiple entries such as a first entry. The first entry may correspond to a page that is made up of multiple chunks. The first entry may include pointers to the multiple chunks stored in the data area. | 05-29-2014 |
20140223104 | VIRTUAL CACHE DIRECTORY IN MULTI-PROCESSOR ARCHITECTURES - Technologies generally described herein relate to cache directories in multi-core processors. Various examples may include, methods, systems, and devices. A first tile may receive a request to transfer a thread from the first tile to a second tile. An instruction may be sent from the first tile to map a virtual cache identifier to identifiers of caches of the first and second tiles. The thread may be transferred from the first tile to the second tile. Thereafter, a request may be generated for a data block. After a determination that the data block is not stored in the second tile's cache, and that the virtual cache identifier is mapped to the first and second cache identifiers, a request may be sent for the data block to the first tile. | 08-07-2014 |
20140237185 | ONE-CACHEABLE MULTI-CORE ARCHITECTURE - Technologies are generally described for methods, systems, and devices effective to implement one-cacheable multi-core architectures. In one example, a multi-core processor that includes a first and second tile may be configured to implement a one-cacheable architecture. The second tile may be configured to generate a request for a data block. The first tile may be configured to receive the request for the data block, and determine that the requested data block is part of a group of data blocks identified as one-cacheable. The first tile may further determine that the requested data block is stored in a first cache in the first tile. The first tile may send the data block from the first cache in the first tile to the second tile, and invalidate the data blocks of the group of data blocks in the first cache in the first tile. | 08-21-2014 |
20140281058 | ACCELERATOR BUFFER ACCESS - Technologies are generally described for methods and systems effective to provide accelerator buffer access. An operating system may allocate a range of addresses in virtual address spaces and a range of addresses in a buffer mapped region of a physical (or main) memory. A request to read from, or write to, data by an application may be read from, or written to, the virtual address space. A memory management unit may then map the read or write requests from the virtual address space to the main or physical memory. Multiple applications may be able to operate as if each application has exclusive access to the accelerator and its buffer. Multiple accesses to the buffer by application tasks may avoid a conflict because the memory controller may be configured to fetch data based on respective application identifiers assigned to the applications. Each application may be assigned a different application identifier. | 09-18-2014 |
20140281336 | MEMORY ALLOCATION ACCELERATOR - Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for allocation of a requested chunk of memory. The request may be received by a memory allocation accelerator configured to be in communication with the processor. The memory allocation accelerator may process the request to identify an address for a particular chunk of memory corresponding to the request and may return the address to the processor. | 09-18-2014 |
20140286179 | HYBRID ROUTERS IN MULTICORE ARCHITECTURES - Technologies are generally described for methods and systems effective to implement hybrid routers in multicore architectures. A first tile may include a processor core, a cache configured to be in communication with the processor core and a router configured to be in communication with the cache. The router may be effective to move data with a packet switching channel or a circuit switching channel. The first tile may include switching logic configured to be in communication with the cache and the router. The switching logic may be effective to receive a routing objective that may relate to energy or delay costs in routing data through the network. The switching logic may select one of the packet switching channel or the circuit switching channel to move the data through the network based on the routing objective. | 09-25-2014 |
20140286191 | HETEROGENEOUS ROUTER CLOCK ASSIGNMENT AND PACKET ROUTING - Technologies generally described herein relate to systems and methods effective to control an operating frequency of routers in a multicore processor. Heterogeneous routers in a multicore processor with different maximum operating frequencies may be clustered together to form groups of routers with homogenous assigned operating frequencies. The groups may be used to identify paths to send packets from a first router to a second router along one or more paths. | 09-25-2014 |
20140366030 | SHARED CACHE DATA MOVEMENT IN THREAD MIGRATION - Technologies are generally described for methods, systems and processors effective to migrate a thread. The thread may be migrated from the first core to the second core. The first and the second core may be configured in communication with a first cache. The first core may generate a request for a first data block from the first cache. In response to a cache miss in the first cache for the first data block, the first core may generate a request for the first data block from a memory. The first core may coordinate with a second cache to store the first data block in the second cache. The thread may be migrated from the second core to a third core. The second core and third core may be configured in communication with the second cache. | 12-11-2014 |
Patent application number | Description | Published |
20100028965 | Method for producing 1,3-propanediol using crude glycerol, a by-product from biodiesel production - The invention discloses a method for producing 1,3-propanediol, comprising the steps of: using crude glycerol, a by-product during the biodiesel production, without further treatment, as the substrate for production of 1,3-propanediol; inoculating a 1,3-propanediol-producing strain in a seed medium containing crude glycerol, a by-product from biodiesel production; adding the seed culture into a fermentation medium containing crude glycerol, a by-product from biodiesel production, and fermenting; maintaining pH in a range of 6.8 to 8.0; and in the end of the fermentation, isolating and purifying 1,3-propanediol. | 02-04-2010 |
20110117617 | METHODS AND GENETICALLY ENGINEERED MICRO-ORGANISMS FOR THE COMBINED PRODUCTION OF PDO, BDO AND PHP BY FERMENTATION - The present invention relates to methods and genetically engineered micro-organisms for the combined production of PDO, BDO, and PHP by fermentation. The micro-organism is characterized in that its D-lactate dehydrogenase gene has been deleted or functionally inactivated, and it comprises heterogenous polynucleotides encoding the Coenzyme A-dependent Aldehyde dehydrogenase and the Polyhydroxyalkanoate synthase. Methods for the construction of such micro-organisms are also disclosed | 05-19-2011 |
20120258521 | METHODS AND GENETICALLY ENGINEERED MICRO-ORGANISMS FOR THE COMBINED PRODUCTION OF PDO, BDO AND PHP BY FERMENTATION - The present invention relates to genetically engineered micro-organisms for the combined production of 1,3-propanediol (PDO), 2,3-butanediol (BDO), and polyhydroxypropionic acid (PHP) by fermentation. In particular, the invention relates to a genetically engineered micro-organism suitable for combined production of PDO, BDO and PHP by fermentation, characterized in that: compared with corresponding wild-type starting micro-organism, the D-lactate dehydrogenase gene in the genetically engineered micro-organism is deleted or functionally inactivated, and the genetically engineered micro-organism comprises a heterogenous polynucleotide encoding the Coenzyme A-dependent Aldehyde dehydrogenase and a heterogenous polynucleotide encoding the Polyhydroxyalkanoate synthase. Methods for the construction of such micro-organisms, and methods for combined production of PDO, BDO and PHP by fermentation of a genetically engineered bacterium are also taught. | 10-11-2012 |
20130290519 | WRITING AND ANALYZING LOGS IN A DISTRIBUTED INFORMATION SYSTEM - Writing logs in a distributed information system are provided. The logs are related to a transaction instance. A method includes retrieving a log proxy instance from a log server. The log proxy instance includes information related to the transaction instance and information related to currently running component in the transaction instance. The method also includes writing the logs for the transaction instance based on the log proxy instance. Aspects of the present invention further provide a method of facilitating writing logs and analyzing logs. Moreover, the embodiments further provide corresponding apparatuses and system. | 10-31-2013 |
20130336484 | TRANSMITTING DEVICE, RECEIVING DEVICE, WIRELESS COMMUNICATION SYSTEM AND METHOD FOR CONTROLLING WIRELESS COMMUNICATION SYSTEM - A transmitting device, a receiving device, a wireless communication system and a method for controlling the wireless communication system are used for creating a secure wireless communication network of a limited area. The transmitting device comprises: one or more transmitters configured to transmit wireless signals, and create the limited area by a coverage scope of the wireless signals; a cryptography key generating unit configured to generate a cryptography key for the wireless signals; a cryptography key encoding unit configured to encode the cryptography key to a cryptography key frame; and a cryptography key scheduling unit configured to schedule the cryptography key frame so as to control the transmitter to transmit the wireless signals including the cryptography key frame. | 12-19-2013 |
20130336485 | METHOD OF CONTROLLING STATES OF MOBILE NODE AND VERIFIER THEREIN FOR RECEIVING SECRET KEY - Disclosed are a verifier used in a mobile node and a method of controlling plural states of the mobile node. The verifier comprises a secret key receiving part configured to listen and receive at least one secret key from at least one secret key transmitter in an area limited Ad-hoc network; a secret key stamp generating part configured to perform calculation on the at least one secret key according to a predetermined verification rule so as to generate a secret key stamp; and a secret key stamp verifying part configured to compare the secret key stamp and a predetermined standard value, wherein, if the secret key stamp is equal to the predetermined standard value, then the secret key is determined as valid, otherwise, the secret key is determined as invalid. | 12-19-2013 |
20140126416 | AREA-LIMITED SELF-ORGANIZED NETWORK MANAGEMENT METHOD, COMMUNICATIONS APPARATUS, AND SYSTEM - Disclosed are an area-limited self-organized wireless network management method, a communication apparatus, and a system. The method comprises a step of, when a communications apparatus which is entering the limited area receives area signals for indicating a specific area in which network nodes are located, determining by the communications apparatus whether the master node exists in the limited area; a step of, if it is determined that the master node exists, performing identity authentication with regard to the master node and letting the communications apparatus itself be a sub node by the communications apparatus; and a step of, if it is determined that the master node does not exist, letting the communications apparatus itself be the master node by the communications apparatus, wherein, the master node is in charge of entering of a new sub node and synchronization of shared secret keys between the network nodes. | 05-08-2014 |
20140219262 | WIRELESS NETWORK AREA LIMITING METHOD AND SYSTEM BASED ON NEAR FIELD COMMUNICATION - Disclosed are a wireless network area limiting method and a wireless network area limiting system based on NFC. The wireless network area limiting method includes a step of adopting a plurality of first NFC hot spot sensors to seamlessly define a limited area having any shape; a step of periodically generating and transmitting an area secret key by a first central control part respectively connected to the plurality of first NFC hot spot sensors; and a step of conducting handshake with the first central control part by a WLAN user equipment, which has a NFC function and is located in the limited area, based on the area secret key received by the WLAN user equipment, so that the first central control part establishes area-limited network communications in the limited area. | 08-07-2014 |
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20120293983 | BACKLIGHT SOURCE AND DISPLAY DEVICE - An embodiment of the disclosed technology discloses a backlight source and a display device. The backlight source including a back plate, an optical film, a light source bracket located between the back plate and the optical film, and a light source mounted onto the light source bracket; the light emitted from the light source is radiated toward the optical film after being reflected by the back plate. | 11-22-2012 |
20140055161 | METHOD FOR DETECTING CROSSTALK OF LIQUID CRYSTAL DISPLAY PANEL - An embodiment of the present invention discloses a method for detecting crosstalk of a liquid crystal display panel, involving detection on a liquid crystal display panel for defect of special crosstalk of the liquid crystal display panel. The method comprises: inputting signals into the liquid crystal display panel to be detected so that a detection pattern is displayed on the liquid crystal display panel to be detected; a gray-scale value for all the pixels in an intermediate region is 0; in other regions a gray-scale value for all the pixels in first pixel groups is the same, a color and gray-scale value for all the pixels in second pixel groups are the same, and the gray-scale value for all the pixels in the second pixel groups differs from that for all the pixels in the first pixel groups; the first pixel groups and the second pixel groups are same in shape, and both are distributed alternatively in both transverse and longitudinal directions in the other regions. | 02-27-2014 |
20140092079 | THIN FILM TRANSISTOR ARRAY SUBSTATE AND LIQUID CRYSTAL DISPLAY APPARATUS THEREOF - The present disclosure provides a Thin Film Transistor Array Substrate and a Liquid Crystal Display apparatus thereof, and relates to the technical field of liquid crystal displaying. The Thin Film Transistor Array Substrate of the present disclosure includes a plurality of gate lines and a plurality of data lines, wherein regions surrounded by the gate lines and the data lines are pixel regions, and wherein a high level common voltage line being used when signal on the data line is at a low level and a low level common voltage lines being used when signal on the data line is at a high level are also arranged in parallel to the gate lines in each of the pixel regions. With the Thin Film Transistor Array Substrate of the present disclosure, the Greenish phenomenon in the existing liquid crystal display apparatus may be effectively solved. | 04-03-2014 |
20140104322 | Method and Device for Adjusting a Display Picture - The present invention discloses a method and a device for adjusting a display picture to solve a problem in the prior art that when Greenish phenomenon of a liquid crystal display screen is alleviated, aperture ratio of the display panel is decreased so that power consumption of the screen is increased. The method for adjusting the display picture includes the steps of: receiving a first clock signal for controlling a data line voltage signal for a pixel of the first color in the display picture and receiving a second clock signal for controlling data line voltage signals for pixels of the other colors; and making a pulse width at high level of the first clock signal smaller than a high level pulse width of the second clock signal, wherein the first color is closer to green than other colors. | 04-17-2014 |
20140132905 | ARRAY SUBSTRATE AND MANUFACTURE METHOD OF THE SAME, LIQUID CRYSTAL DISPLAY PANEL, AND DISPLAY DEVICE - The present invention relates to an array substrate and a manufacture method of the same, a liquid crystal display panel, and a display device, which are relative to a liquid crystal display field. Further, source electrodes and drain electrodes of the array substrate are arranged on different layers. In the manufacture method of the array substrate, the source electrodes and the drain electrodes are formed on different layers by two patterning processes. According to the technical scheme of the present invention, a length of a channel between the source electrodes and the drain electrodes can be decreased as much as possible, thereby increasing a start current I | 05-15-2014 |
20140175448 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof and a display device are provided. As for the method of manufacturing the array substrate, the common electrode and the pixel electrode are formed by a single process simultaneously. | 06-26-2014 |
20140301109 | LIGHT GUIDE PLATE, BACK LIGHT MODULE AND DISPLAY APPARATUS - A light guide plate comprises a transparent light guide plate body; and a plurality of reflection sheets disposed inside the light guide plate body adjacent to a bottom surface of the light guide plate body, wherein a surface of the reflection sheet away from the bottom surface is configured as a reflection surface, regions of the light guide plate body except the reflection sheets are configured as light transmission regions, and the light transmission regions and the reflection sheets are alternately arranged. Since the reflection sheets are provided inside the light guide plate body, the reflection sheet reflects the light which is directed from the one surface and passes through the display panel, and prevents the light, which is directed from the other surface of the display apparatus, from passing through the display panel and interfering with the normal display of the one surface. In this way, the display apparatus can achieve the double-surface display. | 10-09-2014 |
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20140079173 | SHIFTING REGISTER UNIT, SHIFTING REGISTER, DISPLAY APPARATUS AND DRIVING METHOD THEREOF - The embodiments of the present invention provide a shifting register unit, a shifting register, a display apparatus and a driving method thereof, which can solve the problem that the displaying lines close to the bottom of a display panel can not operate normally due to the accumulation of the delays present in the existing shifting register unit and the problem that the lifespan of the third thin-film transistor is affected by the frequent switching-on thereof. The technical solutions allows the trigger signal of the (n+1)th shifting register unit stage to be provided by the first clock signal transmitted from the INPUT_NEXT terminal of the nth shifting register stage, and it can avoid the delay due to the trigger signal of the (n+1)th shifting register unit stage being provided by an output signal of the nth shifting register unit stage, and it can solve the technical problem that the display lines close to the bottom of the display panel can not operate normally due to the accumulation of the delays. Further, after the nth shifting register unit stage outputs the output signal and before the next input signal arrives, the pull-down node remains at high-level under the alternating control of the two clock signals. Thereby, it can be ensured that the pull-up node PU and the output terminal continue to be discharged, and thus the problem that the lifespan of the third thin-film transistor is affected by the frequent switching-on thereof can be solved. | 03-20-2014 |
20140133902 | EXTENSION RECYCLING METHOD BY THE TECHNOLOGY OF BAR EMBEDMENT WITH GLUE FOR WOOD COLUMNS AND APPARATUS THEREOF - The present invention relates to an extension recycling method by the technology of bar embedment with glue for wood columns and an apparatus thereof, the method comprising: classification of short wood, sawing of short wood, drying of short wood, assembling and sorting of short wood, connection in series of short wood under pressure, processing of short wood, and marking of stand columns. The apparatus is a short wood connection machine comprising a main body, rotating rollers, pressing cylinders, pressing plates and a planing frame. By using the present method, short wood can be connected into a strut, so that the abandoned short wood can be recycled to save natural resources. Due to the apparatus and the connecting member of the present invention, the process of connecting short wood into a strut can be completed conveniently, which have the advantages of simple structure, convenient processing and easy manufacturing. | 05-15-2014 |
20140156760 | Method and system for maintaining contact information - Techniques for synchronizing personal contact information with or from different sources are disclosed. Through a website (i.e., a server or system), all fractional personal contact information is consolidated, synchronized, processed or updated. In return, any of the resources may be synchronized to get a copy of the latest version of the contact information. When contacts in a list by a registered user are also registered with the server, any of the contacts may update their respective contact information that can be timely reflected in the list. As a result, the registered user always has a latest version of the contact information for some or all of his/her contacts without even knowing some has already been changed or updated. Based on the contact information, other features including proof delivery of emails, recycling of deleted contacts, a “black” list, contact relationship levels and anonymous email, short messaging and calls are provided. | 06-05-2014 |
Patent application number | Description | Published |
20130150437 | NAPHTHOQUINONES FOR DISEASE THERAPIES - The present invention discloses novel naphtho[2,3-b]furan-4,9-diones and naphtho[2,3-b]thiophene-4,9-diones and methods of making and using the same. The present invention also discloses pharmaceutical compositions comprising novel naphtho[2,3-b]furan-4,9-dione or naphtho[2,3-b]thiophene-4,9-diones for the treatment of various indications including proliferative diseases. | 06-13-2013 |
20130345176 | NOVEL ESTERS OF 4, 9-DIHYDROXY-NAPHTHO [2, 3-b] FURANS FOR DISEASE THERAPIES - The present invention discloses esters of 4,9-dihydroxy-naphtho[2,3-b]furans and methods of making and using the same. The present invention also discloses conversion of the esters into therapeutically active 4,9-dihydroxy-naphtho[2,3-b]furans in vivo. The present invention furthermore discloses pharmaceutical compositions comprising the esters of 4,9-dihydroxy-naphtho[2,3-b]furans for the treatment of various indications including proliferative diseases. | 12-26-2013 |
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20130116628 | Recycled Resin Compositions And Disposable Medical Devices Made Therefrom - Syringe plunger rods comprising an elongate body formed from a composition comprising one or more of virgin material, a sterilization-stable recycled resin and a biobased compositions are described. Plunger rods comprising a plurality of ribs, some of which may have a plurality of openings, are also described. The plunger rods requiring less material while maintaining sufficient structural integrity to function properly. | 05-09-2013 |
20140155826 | Thumb Press Frangible Feature for Re-Use Prevention - Syringe assemblies having a passive disabling system to prevent reuse are provided. According to one or more embodiments, the syringe assembly comprises a barrel, plunger rod and detachable thumb press wherein the plunger rod further comprises flexible locking petals that lock the plunger rod within the barrel and one or more frangible connection or break point at the proximal end of the plunger rod disposed either inside the thumb press or immediately adjacent to the thumb press to separate the thumb press from the main body of the plunger rod when a user applies sufficient proximal force to the plunger rod after it has been locked within the barrel. | 06-05-2014 |
20140296781 | Thumb Press Frangible Feature for Re-Use Prevention - Syringe assemblies having a passive disabling system to prevent reuse are provided. According to one or more embodiments, the syringe assembly comprises a barrel, plunger rod and detachable thumb press wherein the plunger rod further comprises flexible locking petals that lock the plunger rod within the barrel, a ramp disposed adjacent to the locking element, and one or more frangible connection or break point at the proximal end of the plunger rod disposed either inside the thumb press or immediately adjacent to the thumb press to separate the thumb press from the main body of the plunger rod when a user applies sufficient proximal force to the plunger rod after it has been locked within the barrel. | 10-02-2014 |
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20120014313 | OPPORTUNISTIC USE OF WIRELESS NETWORK STATIONS AS REPEATERS - Implementation of opportunistic use of stations in a wireless network as repeaters is described. In one implementation, a station detects the existence of rate anomaly in a wireless network. In response to the rate anomaly, the station may transform into a software repeater for certain other neighboring stations. The repeater function allows for the relaying of packets sent by these neighboring stations to the access point and vice versa. The other neighboring stations, owing to their relative proximity to the repeater station, transmit data at a higher rate to the repeater station. Thus, the removal of the slower stations reduces clogging of the access point and increases the overall data rate within the wireless network. Further, a zero-overhead network coding protocol may be implemented in conjunction with the repeater function to increase capacity of the wireless network. | 01-19-2012 |
20120151382 | GENERATING AND MANAGING ELECTRONIC DOCUMENTATION - Some implementations provide a user interface for generating an electronic document. An external component may be launched within the user interface for accessing external data, and context data of the current document may be provided to the external component. The external data that corresponds to the context data for the document may be displayed within the user interface, such as for enabling a user to interact with the data and/or include a portion of the data in the document. | 06-14-2012 |
20130219277 | Gesture and Voice Controlled Browser - A computer readable storage medium stores instructions defining a mobile device browser. The mobile device browser supports direct command inputs and executable instructions to correlate a proxy command to a selected direct command input. The proxy command is alternately expressed as a gesture and a voice command. The selected direct command input is automatically executed by the mobile device browser. | 08-22-2013 |