Patent application number | Description | Published |
20080229027 | PREFETCH CONTROL DEVICE, STORAGE DEVICE SYSTEM, AND PREFETCH CONTROL METHOD - A prefetch control device controls prefetching of read-out data into cache memory which improves efficiency of data reading from a storage device by caching data passed between the storage device and a computing device, determines whether data read out from the storage device to the computing device is sequentially accessed data or not, decides a prefetch amount for the read-out data in accordance with a predetermined condition if the read-out data is determined to be sequentially accessed data, and prefetches the read-out data of the prefetch amount. | 09-18-2008 |
20080229071 | PREFETCH CONTROL APPARATUS, STORAGE DEVICE SYSTEM AND PREFETCH CONTROL METHOD - A prefetch control apparatus includes a prefetch controller for controlling prefetch of read data into a cache memory caching data to be transferred between a computer apparatus and a storage device, and which enhances a read efficiency of the read data from the storage device, a sequentiality decider for deciding whether the read data that are read from the storage device toward the computer apparatus are sequential access data, a locality decider for deciding whether the read data have locality of data arrangement in the predetermined storage area, in a case where the read data that are read from the storage device toward the computer apparatus have been decided not to be sequential access data, and a prefetcher for prefetching the read data in a case where the read data has the locality of the data arrangement. | 09-18-2008 |
20100211732 | COPY CONTROL APPARATUS - A copy control apparatus for controlling a copy process between disks includes a copy process execution unit, a data capacity measuring unit, and a changing unit. The copy process execution unit executes the copy process between disks by securing a storage area on a cache. The data capacity measuring unit measures a data capacity contained in a write request accepted from a host system during execution of the copy process between disks by the copy process execution unit. The changing unit changes a capacity of the storage area secured by the copy process execution unit in accordance with the data capacity measured by the data capacity measuring unit. | 08-19-2010 |
Patent application number | Description | Published |
20080228551 | PERSONNEL ASSIGNMENT OPTIMIZATION PROGRAM, PERSONNEL ASSIGNMENT OPTIMIZATION METHOD, AND PERSONNEL ASSIGNMENT OPTIMIZATION DEVICE - An optimization control part controls as an optimum method that optimizes a personnel assignment with an optimum gradient method by simulating with a simulator. An increase and decrease personnel assignment calculation part calculates the increase and decrease personnel assignment by using an approximation model to find the next tentative optimum solution and to generate an initial value by using the approximation model. In addition, the personnel assignment information storage stores the necessary information to optimize the personnel assignment, and the simulator, the optimization control part and the increase and decrease personnel assignment calculation part refer to the information in the personnel assignment information storage part, update it and perform processing. | 09-18-2008 |
20090304174 | ACCESS-FREQUENCY ESTIMATING APPARATUS AND COMPUTER PRODUCT - An access-frequency estimating apparatus includes a storage unit that stores hours outside operating hours and for which a second-degree derivative of access frequency distribution for contact centers whose business is similar to that of a contact center subject to estimation is nearly 0, and a coefficient indicating relation between access frequency during operating hours of the other contact centers and access frequency outside the operating hours; an acquiring unit that acquires past access frequencies for operating hours of the contact center; an extracting unit that extracts, from the storage unit, a coefficient expressing relation between the access frequencies for the operating hours and an arbitrary hour outside the operating hours; a first calculating unit that calculates an estimated access frequency for the arbitrary hour of the contact center, based on the past access frequencies acquired and the coefficient; and an output unit that outputs the estimated the access frequency calculated. | 12-10-2009 |
20100082948 | CHANNEL COMMAND WORD PRE-FETCHING APPARATUS - In a CCW fetching section, for each input/output device being a control objective, a result prediction table in which prediction values of status values to be returned from an input/output device as execution results of CCW commands, is referred to. Then, based on the prediction values, commands being pre-fetching objectives are pre-fetched from a CCW program stored in a memory, and transmitted to a CCW executing section. On the other hand, in the CCW executing section, the pre-fetched commands are sequentially executed, and the actual status values as the execution results are received from the input/output device. Then, when the received actual status values are not same as the predicted status values, success or failure in prediction is notified to the CCW fetching section, and also, the result prediction table is updated in the CCW fetching section. | 04-01-2010 |
Patent application number | Description | Published |
20100332930 | STORAGE CIRCUIT, INTEGRATED CIRCUIT, AND SCANNING METHOD - A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied. | 12-30-2010 |
20130163356 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of memory cells, a plurality of receivers, each of the plurality of receivers being provided for a corresponding one of a plurality of units set by dividing the plurality of memory cells in a unit, and each of the plurality of receivers receiving a test result of the corresponding one of the plurality of units, and a controller that reads out a plurality of test results from the plurality of receivers. | 06-27-2013 |
20140068193 | SEMICONDUCTOR DEVICE AND MEMORY TEST METHOD - An address range of an L2 cache is divided into sets of a predetermined number of ways. A RAM-BIST pattern generating unit generates a memory address corresponding to a way, a test pattern, and an expected value with respect to the test pattern. The L2 cache and an XOR circuit write the test pattern to a memory address in accordance with the test pattern, read data from the memory address to which the test pattern is written, and compares the read data with the expected value. A decode unit generates a selection signal for each way of the L2 cache by using a memory address. A determination latch stores, by using a selection signal and in a way corresponding to each memory address, a comparison result with respect to the memory address, a scan-out being performed on the comparison result stored in each of the ways in a predetermined order. | 03-06-2014 |