Patent application number | Description | Published |
20090295452 | BOOSTING CIRCUIT - A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≦K≦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented. | 12-03-2009 |
20090295464 | BOOSTER CIRCUIT - Analog comparison circuits are provided, each of which compares the potentials of the same stage of a first boosting cell row and a second boosting cell row and selecting and outputting the lower potential. The P-well potentials of switching devices having a triple-well structure are controlled using the output potentials of these analog comparison circuits. As a result, the amplitude of the P-well potential can be suppressed and a common P-well region can be arranged. | 12-03-2009 |
20100007408 | INTERNAL VOLTAGE GENERATING CIRCUIT - An output terminal of a first boost circuit is connected to a second boost circuit. After the second boost circuit is started up, a boost clock frequency of the second boost circuit is reduced. A time required to start up the second boost circuit is reduced, and in addition, a current supply capability of the first boost circuit is increased after the second boost circuit is started up. When the second boost circuit is driven, output voltages of the first and second boost circuits are stably supplied without instantaneously changing the output voltage of the first boost circuit. | 01-14-2010 |
20100277228 | BOOSTER CIRCUIT - A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared. | 11-04-2010 |
20110025381 | MULTI-PHASE CLOCK DIVIDER CIRCUIT - A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal. | 02-03-2011 |
20110063018 | BOOSTER CIRCUIT - In a booster circuit which is operated with a two-phase clock and in which a plurality of (M≧4) lines of boosting cells constitute a unit, a boosting cell in the K-th line (1≦K≦M) is controlled, depending on the voltage of the input terminal of a boosting cell in the KA-th line (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). As a result, a charge transfer transistor can transition from the conductive state to the non-conductive state before a clock input to the boosting cell in the K-th line transitions from low to high and then boosting operation is performed. As a result, the backflow of charge via the charge transfer transistor can be reduced or prevented. | 03-17-2011 |
20110169557 | CHARGE PUMP CIRCUIT - Each of a plurality of pump stages has an input node and an output node and performs a charge pump operation in response to any one of the first and second clock signals. The plurality of pump stages include a first pump stage, in which a charge transfer transistor is connected between the input node and the output node. One end of a pump capacitor is connected to the output node, and the other end is supplied with one of the first and second clock signals corresponding to the first pump stage. A connection switcher connects to the gate of the charge transfer transistor any one of the output node of a pump stage which is supplied with one of the clock signals corresponding to the first pump stage and the input node of a pump stage which is supplied with the other clock signal not corresponding to the first pump stage and which is included in a pump stage row not including the first pump stage. | 07-14-2011 |
20110241635 | SEMICONDUCTOR INTEGRATED CIRCUIT AND BOOSTER CIRCUIT INCLUDING THE SAME - A semiconductor integrated circuit includes: a first transistor and a second transistor connected in series between a first voltage and a second voltage; a first inverter configured to control the first transistor; a second inverter configured to control the second transistor; and a current source, wherein the current source is connected in series with at least one of the first inverter or the second inverter. | 10-06-2011 |
20130124888 | NONVOLATILE STORAGE SYSTEM, POWER SUPPLY CIRCUIT FOR MEMORY SYSTEM, FLASH MEMORY, FLASH MEMORY CONTROLLER, AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories. | 05-16-2013 |
20130336067 | NONVOLATILE STORAGE SYSTEM, POWER SUPPLY CIRCUIT FOR MEMORY SYSTEM, FLASH MEMORY, FLASH MEMORY CONTROLLER, AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories. | 12-19-2013 |
20140104933 | SEMICONDUCTOR MEMORY - Provided is a semiconductor memory in which it is easier to read a read margin when an ambient temperature changes. The semiconductor memory includes: a memory cell including a first variable resistance element having variable electric resistance; a first reference cell including a second variable resistance element having variable electric resistance, and serving as a point of reference for a magnitude of electric resistance of the memory cell; and a second reference cell serving as a point of reference for a magnitude of electric resistance of the first reference cell, in which a first temperature coefficient of the first variable resistance element and a second temperature coefficient of the second variable resistance element have the same polarity. | 04-17-2014 |
20140112043 | SWITCHING POWER SUPPLY APPARATUS - A switching power supply apparatus which receives AC voltage and includes: a transformer including a primary winding and a secondary winding; a first bidirectional switch connected in series with the primary winding; and a Snubber circuit connected in parallel with the primary winding. The AC voltage is applied to a series circuit which includes the primary winding and the first bidirectional switch. The Snubber circuit includes a second bidirectional switch for controlling the first bidirectional switch. | 04-24-2014 |