Patent application number | Description | Published |
20150102826 | DESIGN STRUCTURES AND METHODS FOR EXTRACTION OF DEVICE CHANNEL WIDTH - Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths. | 04-16-2015 |
20150318217 | MIXED N/P TYPE NON-PLANAR SEMICONDUCTOR STRUCTURE WITH MULTIPLE EPITAXIAL HEADS AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape. | 11-05-2015 |
20150318351 | MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. | 11-05-2015 |
20150332963 | T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE - A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling. | 11-19-2015 |
20150332972 | FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES - A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure. | 11-19-2015 |
20150340501 | FORMING INDEPENDENT-GATE FINFET WITH TILTED PRE-AMORPHIZATION IMPLANTATION AND RESULTING DEVICE - Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET. | 11-26-2015 |
20150380515 | MULTI-PHASE SOURCE/DRAIN/GATE SPACER-EPI FORMATION - Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer. | 12-31-2015 |
20160035723 | MACRO DESIGN OF DEVICE CHARACTERIZATION FOR 14NM AND BEYOND TECHNOLOGIES - The disclosure provides methods and devices for separately determining the channel resistance and the extension resistance of a FinFET. An exemplary embodiment includes forming first and second fins parallel to each other, forming at least one fin portion, connecting the first and second fins, forming a gate perpendicular to the first and second fins, over the at least one fin portion, forming a first source and a first drain over the first fin at opposite sides of the gate, and forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate, wherein each of the first and second sources and first and second drains includes an extension region. | 02-04-2016 |