Patent application number | Description | Published |
20120247529 | SOLAR CELL MODULES AND METHODS OF MANUFACTURING THE SAME - Back contact solar cell modules and methods of manufacturing the same. The solar cell module comprises a back surface with a plurality of first electrodes and a plurality of second electrodes formed thereon, the plurality of first electrodes and the plurality of second electrodes being of opposite polarities, the back surface being configured to form an electric field thereon of the opposite polarity as the plurality of first electrodes; a first connecting strip electrically connecting the plurality of first electrodes; and an insulative member between the back surface and the first connecting strip. | 10-04-2012 |
20120298192 | LIGHT TO CURRENT CONVERTER DEVICES AND METHODS OF MANUFACTURING THE SAME - Light to current converter devices, such as solar cells, are disclosed. The devices may include via holes extending through the cell substrate and may include through-hole electrodes within the via holes. The through-hole electrodes may be made from one or more materials and may be hollow, partially hollow, or fully filled. Front and rear electrodes may also be formed on the device and can be made of the same or different materials as the through-hole electrode. The devices may include emitters located only on the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, or located on the top surface and full inner surface of the via holes. Processes for making light to current converter devices are also disclosed. | 11-29-2012 |
20120301997 | METHODS OF MANUFACTURING LIGHT TO CURRENT CONVERTER DEVICES - Processes for making light to current converter devices are provided. The processes can be used to make light to current converter devices having P-N junctions located on only the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, located on the top surface and full inner surface of the via holes, or located on the top surface, full inner surface of the via holes, and a portion of the bottom surface of the cell. The processes may isolate the desired P-N junction by etching the emitter, forming a via hole after forming the emitter, using a barrier layer to protect portions of the emitter from etching, or using a barrier layer to prevent the emitter from being formed on portions of the substrate. | 11-29-2012 |
20150037924 | METHODS OF MANUFACTURING LIGHT TO CURRENT CONVERTER DEVICES - Processes for making light to current converter devices are provided. The processes can be used to make light to current converter devices having P-N junctions located on only the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, located on the top surface and full inner surface of the via holes, or located on the top surface, full inner surface of the via holes, and a portion of the bottom surface of the cell. The processes may isolate the desired P-N junction by etching the emitter, forming a via hole after forming the emitter, using a barrier layer to protect portions of the emitter from etching, or using a barrier layer to prevent the emitter from being formed on portions of the substrate. | 02-05-2015 |
Patent application number | Description | Published |
20150102826 | DESIGN STRUCTURES AND METHODS FOR EXTRACTION OF DEVICE CHANNEL WIDTH - Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths. | 04-16-2015 |
20150318217 | MIXED N/P TYPE NON-PLANAR SEMICONDUCTOR STRUCTURE WITH MULTIPLE EPITAXIAL HEADS AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape. | 11-05-2015 |
20150318351 | MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. | 11-05-2015 |
20150332963 | T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE - A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling. | 11-19-2015 |
20150332972 | FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES - A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure. | 11-19-2015 |
20150340501 | FORMING INDEPENDENT-GATE FINFET WITH TILTED PRE-AMORPHIZATION IMPLANTATION AND RESULTING DEVICE - Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET. | 11-26-2015 |
20150380515 | MULTI-PHASE SOURCE/DRAIN/GATE SPACER-EPI FORMATION - Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer. | 12-31-2015 |
20160035723 | MACRO DESIGN OF DEVICE CHARACTERIZATION FOR 14NM AND BEYOND TECHNOLOGIES - The disclosure provides methods and devices for separately determining the channel resistance and the extension resistance of a FinFET. An exemplary embodiment includes forming first and second fins parallel to each other, forming at least one fin portion, connecting the first and second fins, forming a gate perpendicular to the first and second fins, over the at least one fin portion, forming a first source and a first drain over the first fin at opposite sides of the gate, and forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate, wherein each of the first and second sources and first and second drains includes an extension region. | 02-04-2016 |
20160049468 | PRODUCT COMPRISED OF FINFET DEVICES WITH SINGLE DIFFUSION BREAK ISOLATION STRUCTURES - An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure. | 02-18-2016 |
20160118500 | FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM - A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin. | 04-28-2016 |
20160126316 | TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF - Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure. | 05-05-2016 |
20160126336 | METHOD OF IMPROVED CA/CB CONTACT AND DEVICE THEREOF - Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal. | 05-05-2016 |
Patent application number | Description | Published |
20140264613 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure. | 09-18-2014 |
20150091097 | HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT - Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor. | 04-02-2015 |
20150093878 | FINFET FABRICATION METHOD - Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins. | 04-02-2015 |
20150333062 | FINFET FABRICATION METHOD - Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins. | 11-19-2015 |
Patent application number | Description | Published |
20150123568 | LOAD DRIVE CIRCUIT, LOAD DRIVE METHOD, AND LUMINAIRE - A load drive circuit may include a DC power source configured to provide a DC output voltage for at least one load based on an output voltage of an AC/DC converter, the DC output voltage having a ripple, a variable resistance module connected to the load, a ripple reduction module that generates, based on a reference voltage and a feedback signal from the load, a variable resistance adjusting signal for adjusting the resistance of the variable resistance module so as to reduce a ripple of the load current, wherein the reference voltage is generated based on the DC output voltage, and a reference voltage adjusting module that adjusts the average value of the reference voltage based on the variable resistance adjusting signal, so as to make the average value of the reference voltage approach the average value of the feedback signal as much as possible. | 05-07-2015 |
20160073459 | LED LAMP DEVICE - Various embodiments relate to an LED lamp device. According to various embodiments, an LED lamp device is provided, including an LED unit for emitting light, a driving unit for driving the LED unit, such that the LED unit emits light at an operating point, and a resonance unit for receiving an input, providing AC power to the driving unit, and protecting the driving unit and the LED unit from being damaged by the input. | 03-10-2016 |