Patent application number | Description | Published |
20140017916 | FOUR IN ONE ELECTRICAL CONNECTOR PLUG - An electrical connector plug includes a casing an output/input port mounted having multiple upper terminals and multiple lower terminals, a trough defined between the upper terminals and the lower terminals, a circuit board inserted in the trough of the casing and having, a metal plate electrically connected to the ground terminal and a metal housing to entirely enclose the casing and to electrically connect to the metal plate such that the metal plate is able to transmit electromagnetic interference out via the metal housing. | 01-16-2014 |
20140024261 | FOUR IN ONE ELECTRICAL CONNECTOR SOCKET - An electrical connector socket includes a casing, a main body received in the casing, a first power contact terminal one distal end of which is mounted inside the power transmission body, a first power detect terminal, a second power detect terminal, a second power contact terminal, a ground terminal, upper terminals, lower terminals, an upper enclosure provided to enclose the bents of the upper terminals and a lower enclosure provided to enclose the bents of the lower terminals and to combine with the upper enclosure. | 01-23-2014 |
20150349466 | ELECTRICAL CONNECTOR - Electrical connector includes an insulative body, first and second terminals, shielding housing, and adhesive. The insulative body has a tongue piece and a base having first and second positioning grooves. Each of the first terminals has a first positioning part received in the insulative body, a first electrical contact part exposed from the tongue piece, and a first bonding part accommodated in a corresponding one of the first positioning grooves and protruding from the base. Each of the second terminals has a second positioning part received in the base, a second electrical contact part exposed from the tongue piece, and a second bonding part accommodated in a corresponding one of the second positioning grooves and protruding from the base. Adhesive is injected into the first and second positioning grooves to encapsulate the first bonding parts in the first positioning grooves and the second bonding parts in the second positioning grooves. | 12-03-2015 |
Patent application number | Description | Published |
20080308710 | Mold with a returning apparatus - A mold with a returning apparatus includes a female and a male mold. The male mold has a fix plate with a through bore, a lower eject plate, an upper eject plate, an eject pin fixed to the upper eject plate, and a returning apparatus. The returning apparatus has a pull rod and a returning portion having a gap. The pull rod defines a top at one end thereof, a surrounding portion adjacent to the top, and a compression formed between the top and the surrounding portion. The gap has a first cavity at an upper portion thereof, a second cavity communicating with the first cavity at a lower portion thereof, and a step formed therebetween. The size of the first cavity is bigger than the second cavity. The top is received in the first cavity, the surrounding portion is received in the second cavity, and the compression abuts against the step. | 12-18-2008 |
20090181119 | Lateral core-pulling mechanism of mold - A lateral core-pulling mechanism of mold includes a cavity plate, a cavity insert configured in the cavity plate and defining a shaping recess, and a core-pulling body including a first slide module longitudinally movably disposed in the front of the cavity plate, an angular pin, and two second slide modules movably disposed at two sides of the cavity insert. The first slide module defines an inclined hole, a first shaping core inserted into the shaping recess and two first guide surfaces at two side edges thereof. The angular pin has an inclined block inclining forward and movably received in the inclined hole to drive the first slide module to move forward or backward. The second slide module defines a second shaping core inserted into the shaping recess and a second guide surface slidably matching the corresponding first guide surface to drive the second slide module to move sideward. | 07-16-2009 |
Patent application number | Description | Published |
20150123254 | CHIP SCALE DIODE PACKAGE NO CONTANING OUTER LEAD PINS AND PROCESS FOR PORDUCING THE SAME - A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection. | 05-07-2015 |
20150200147 | MINIATURIZED SMD DIODE PACKAGE AND PRSCESS FOR PRODUCING THE SAME - A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect. | 07-16-2015 |
20160035697 | MINIATURIZED SMD DIODE PACKAGE AND PROCESS FOR PRODUCING THE SAME - A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect. | 02-04-2016 |
Patent application number | Description | Published |
20100117271 | Process for producing zinc oxide varistor - A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism. | 05-13-2010 |
20120208040 | STRUCTURE OF MULTILAYER CERAMIC DEVICE - A multilayer ceramic device comprises a laminated ceramic body having opposite end surfaces, a pair of conductive electrodes each respectively attached to one end surface of the laminated ceramic body and a plurality of alternately staggered internal electrodes within the laminated ceramic body configured in an alternating manner and each electrically connected to the corresponding conductive electrodes respectively; each conductive electrodes of the multilayer ceramic device is further covered with a solder paste layer so that the multilayer ceramic device is thus made without any plating step and no need of treating waste liquid nickel or waste liquid tin as well as no problem of environmental pollution caused by plating solution, thereby lowering manufacturing costs and reducing processing time. | 08-16-2012 |
20130011963 | PROCESS FOR PRODUCING ZINC OXIDE VARISTOR - A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm. | 01-10-2013 |
Patent application number | Description | Published |
20100015776 | Shallow Trench Isolation Corner Rounding - A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration. | 01-21-2010 |
20110012210 | Scaling EOT by Eliminating Interfacial Layers from High-K/Metal Gates of MOS Devices - An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer. | 01-20-2011 |
20110193178 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 08-11-2011 |
20110241084 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 10-06-2011 |
20130043507 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 02-21-2013 |
20130196478 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 08-01-2013 |
20140187011 | Methods for Forming FinFETs with Self-Aligned Source/Drain - A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess. | 07-03-2014 |
20140187013 | Methods for Forming FinFETs Having Multiple Threshold Voltages - A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively. | 07-03-2014 |
20140252475 | FinFETs and Methods for Forming the Same - A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned. | 09-11-2014 |
20140264494 | Metal-Oxide-Semiconductor Field-Effect Transistor with Metal-Insulator Semiconductor Contact Structure to Reduce Schottky Barrier - A method includes depositing a first metal layer on a native SiO | 09-18-2014 |
Patent application number | Description | Published |
20120231655 | ELECTRICAL CONNECTOR - An electrical connector includes an insulating housing, and a plurality of electrical contacts assembled in the insulating housing respectively. At least two of the electrical contacts having the same transmitting action are short connected together in the process of manufacturing the electrical contacts. So the process of utilizing a wire to achieve a short connection between the corresponding electrical contacts, as described in the prior art, is omitted, and it saves a lot of manpower and material resources, and further simplifies the process for achieving the short connection effect. | 09-13-2012 |
20120322288 | ELECTRICAL CONNECTOR AND TERMINAL THEREOF - An electrical connector includes an insulating body and a plurality of terminals assembled in the insulating body. The terminal has a fastening strip of which a bottom end is bent towards one side of the fastening strip and then protrudes rearward to form a soldering portion. A top end of the fastening strip is bent towards the other side of the fastening strip and then extends forward to form a first contact portion which has a front end thereof arched upward to project out of the insulating body for electrically connecting with one circuit. A second contact portion is formed at a substantial middle of a front edge of the fastening strip and further exposed outside the insulating body for electrically connecting with another circuit. | 12-20-2012 |
20120325629 | Tilt Switch - A tilt switch includes an insulating housing having a receiving chamber and a connecting cavity between which a ring-shaped step is formed, electrical terminals each having a support arm of platy shape inserted upward into the connecting cavity, a switching ball made of conductive materials and rollably placed in the receiving chamber, and an insulating cover removably covered on the insulating housing to restrain the switching ball in the insulating housing. The support arms are arranged at regular intervals around the center axis of the connecting cavity. The ring-shaped step has a top face substantially perpendicular to two vertical periphery surfaces of the connecting cavity and the receiving chamber. The switching ball needs to roll over the ring-shaped step having a hard span when the tilt switch changes working states thereof among a closed state, a shorted state and an open state. | 12-27-2012 |
20130001053 | TILT SWITCH - A tilt switch includes an insulating housing having a receiving chamber and a connecting cavity smaller than the receiving chamber in diameter to form a step therebetween, electrical terminals penetrating through the insulating housing to project into the connecting cavity, an insulating cover removably covered on the insulating housing, and a switching ball made of conductive materials and rollably placed between the insulating housing and the insulating cover. The step has a top face perpendicular to periphery surfaces of the connecting cavity and the receiving chamber. The switching ball needs to roll over the step having a hard span when the tilt switch changes working states between a closed state realized by the switching ball projecting into the connecting cavity to simultaneously connect with the electrical terminals, and an open state realized by tilting the tilt switch to disconnect the switching ball from at least one electrical terminal. | 01-03-2013 |
20130102193 | SHIELDING SHELL OF A CONNECTOR - A shielding shell includes a front shell curved from a metal plate and having a base board and two side boards, and a rear shell having a base plate of which a front edge is connected with a rear edge of the base board. Two side plates extend downward from two opposite side edges of the base plate and each is connected with a rear edge of the side board of the front shell by virtue of a strengthening structure. The strengthening structure includes a first strengthening arm extending towards the corresponding side plate from a rear edge of the side board, and a second strengthening arm extending towards the corresponding side board from a front edge of the side plate to be buckled with the first strengthening arm so as to secure the side plate and the corresponding side board together. | 04-25-2013 |
20130164977 | ELECTRICAL CONNECTOR - An electrical connector includes an insulating housing, a plurality of terminals assembled in the insulating housing, and a shielding shell curved from a metal plate to show a hollow barrel shape and enclose the insulating housing. An inserting space is formed between a front of the insulating housing and periphery inner sides of a front of the shielding shell, and has a free open front end for inserting a mating connector therefrom into the inserting space. The terminals project into the inserting space to connect with the mating connector. A pair of elastic fool-proofing elements is formed at two opposite bottom corners of the open front end of the shielding shell and each shows an arc shape from a front view. Two cambered faces of the elastic fool-proofing elements face each other for guiding the insertion of the mating connector and further elastically resisting against the mating connector. | 06-27-2013 |
20130189877 | CABLE CONNECTOR - A cable connector connecting between a cable and a mated connector includes an insulating housing, a plurality of terminals disposed in the insulating housing, an inner shielding shell and an outer shielding shell surrounding the inner shielding shell. The insulating housing has a base portion and a tongue portion protruded forward from a front of the base portion. The insulating housing defines a plurality of passages concaved inward in periphery outer sides thereof and each extending along a front-to-rear direction. The inner shielding shell has a top plate, two end plates and a bottom plate which are interconnected to form an accommodating space thereamong for receiving the base portion therein. A plurality of contact strips are distributed along a front periphery of the inner shielding shell and restrained in the corresponding passages to electrically connect with the mated connector. | 07-25-2013 |
20130189878 | CABLE-TO-BOARD CONNECTOR - A cable-to-board connector includes a plug connector and a receptacle connector. The plug connector includes a plug housing, a plurality of plug terminals disposed in the plug housing, and a plug shielding shell surrounding the plug housing. At least two buckling blocks protrude oppositely from two outer surfaces of two opposite sides of the plug shielding shell. The receptacle connector includes a receptacle housing, a plurality of receptacle terminals disposed in the receptacle housing, and a receptacle shielding shell defining a receptacle accommodating space therein. The receptacle housing is inserted in a front of the receptacle accommodating space. Each side of the receptacle shielding shell defines at least one second buckling hole. A rear inner periphery of the receptacle shielding shell is attached to a front outer periphery of the plug shielding shell with the buckling blocks being buckled in the second buckling holes. | 07-25-2013 |
Patent application number | Description | Published |
20130069125 | SEMICONDUCTOR DEVICE, ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region. | 03-21-2013 |
20130099297 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device electrically connected between a pad and an internal circuit is provided and includes a capacitor, a first resistor, a voltage-drop element and an NMOS transistor. A first end of the capacitor is electrically connected to the pad. A first end of the first resistor is electrically connected to a second end of the capacitor, and a second end of the first resistor is electrically connected to ground. The NMOS transistor and the voltage-drop element are connected in series between the pad and the ground, a gate of the NMOS transistor is electrically connected to the second end of the capacitor, and a bulk of the NMOS transistor is electrically connected to the ground. | 04-25-2013 |
20130134479 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal. | 05-30-2013 |
Patent application number | Description | Published |
20140109958 | METHOD OF IN-SITU FABRICATING INTRINSIC ZINC OXIDE LAYER AND THE PHOTOVOLTAIC DEVICE THEREOF - A method of fabricating a photovoltaic device includes forming an absorber layer for photon absorption over a substrate, forming a buffer layer above the absorber layer, wherein both the absorber layer and the buffer layer are semiconductors, and forming a layer of intrinsic zinc oxide above the buffer layer through a hydrothermal reaction in a solution of a zinc-containing salt and an alkaline chemical. | 04-24-2014 |
20140352751 | SOLAR CELL OR TANDEM SOLAR CELL AND METHOD OF FORMING SAME - A solar cell includes an absorber layer, a buffer layer on the absorber layer, a front contact layer where a glass substrate, a back contact layer on the glass substrate, the absorber layer on the back contact layer, the buffer layer, and the front contact layer are manufactured as a first module at a temperature exceeding 500 degrees Celsius. The solar further includes an extracted portion from the first module where the extracted portion includes the absorber layer, the buffer layer, and the front contact layer, and where the extracted portion is applied to a flexible substrate or other substrate. | 12-04-2014 |
20150079717 | APPARATUS AND METHODS FOR FABRICATING SOLAR CELLS - A method for fabricating a solar cell generally comprises delivering a solar cell substructure to a chamber. Electromagnetic radiation is generated using a wave generating device that is coupled to the chamber such that the wave generating device is positioned proximate to the solar cell substructure. The electromagnetic radiation is applied onto at least a portion of the solar cell substructure to facilitate the diffusion of at least one metal element through at least a portion of the solar cell substructure such that a semiconductor interface is formed between at least two different types of semiconductor materials of the solar cell substructure. | 03-19-2015 |
20150114445 | TRANSPARENT COVER FOR SOLAR CELLS AND MODULES - A solar cell device and a method of fabricating the same are described. The method of fabricating a solar cell includes forming a photovoltaic substructure including a substrate, back contact, absorber and buffer, forming a transparent cover separate from the photovoltaic substructure including a transparent layer and a plasmonic nanostructured layer in contact with the transparent layer, and adhering the transparent cover on top of the photovoltaic substructure. The plasmonic nanostructured layer can include metal nanoparticles. | 04-30-2015 |
20150162459 | SOLAR CELL ANTI REFLECTIVE COATING AND WET CHEMICAL METHOD FOR FORMING THE SAME - Provided are methods for forming antireflective layers on solar cells using wet chemical processes and solar cells with anti-reflective layers formed of ZnO based nanorods. Self-assembling ZnO nanorods are generated in the chemical solution without any catalysts. The nanorods are formed to different shapes such as hexagonal, cubic, and circular in cross-section. The refractive index of the ARC layer formed of the nanorods is modulated by controlling the diameter and length of the nanorods by controlling the Molarity of the solution used to form the nanorods. A correlation is established between the refractive index and solution Molarity and a solution is prepared with the desired Molarity. The nanorods are formed from HMT ([CH | 06-11-2015 |
Patent application number | Description | Published |
20140109897 | APPARATUS FOR CONUTIOUSLY PROCESSING LIGNOCELLULOSIC MATERIAL - Disclosed is an apparatus for continuously processing a lignocellulosic material, and particularly to an apparatus for continuously processing a lignocellulosic material by using of a single-stage or two-stage pretreatment processing with related to the acid-catalyzed steam explosion processing combined with dilute acid hydrolysis and steam explosion, in which parameters are adjusted to maintain in a state where lignocellulosic material feeding, acid mixing pre-heating, dilute acid hydrolysis reaction, steam explosion and flash discharge, to solid and liquid separation are simultaneously and continuously operated, so as to achieve in the results of acquiring xylose hydrolyzate by hydrolyzing hemicellulose, destroying lignocellulosic material structure, increasing surface area and porosity. | 04-24-2014 |
20140116014 | CYCLONE DEVICE FOR SEPARATING STICKY MATERIAL FROM GAS STREAM - A cyclone device for separating a sticky material from a gas stream, comprising a tin body; an introducing tube, connected to the tin body and arranged on a facet of the tin body; a central exhaust pipe, arranged within the tin body on a top position thereof, a conical tin connected to a bottom of the tin body at one end and having a particle discharging exit at the other end; a supporting wheel set, arranged within the tin body and adjacent to an end of the conical tin; and a scraping mechanism arranged movably on the supporting wheel set. | 05-01-2014 |
Patent application number | Description | Published |
20100117271 | Process for producing zinc oxide varistor - A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism. | 05-13-2010 |
20120057265 | ZINC-OXIDE SURGE ARRESTER FOR HIGH-TEMPERATURE OPERATION - A ZnO surge arrester for high-temperature operation is characterized in that a grain boundary layer between ZnO grains thereof contains a BaTiO | 03-08-2012 |
20130011963 | PROCESS FOR PRODUCING ZINC OXIDE VARISTOR - A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm. | 01-10-2013 |