Patent application number | Description | Published |
20080284351 | Ignition Module for Gas Discharge Lamp - The present invention relates to an ignition module for a gas discharge lamp, said ignition module comprising: a first module for generating a first series of pulse from a low frequency driving signal, a second module for generating a second series of pulse from a high frequency driving signal, and a superposing and boosting module for boosting module for superposing and increasing said first series of pulse and said second series of pulse so as to generate an output pulse intended to break down the gas in said gas discharge lamp. Via this invention, a high effective OCV can be easily obtained without increasing the DCBUS, and the ignition of the gas discharge lamp is improved. | 11-20-2008 |
20090086801 | Method for reliable injection of deterministic jitter for high speed transceiver simulation - A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization. | 04-02-2009 |
20090086872 | Method for binary clock and data recovery for fast acquisition and small tracking error - A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value. | 04-02-2009 |
20090161452 | Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design - A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced. | 06-25-2009 |
20090167443 | Digitally compensated highly stable holdover clock generation techniques using adaptive filtering - A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider. | 07-02-2009 |
20100246739 | METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS - A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency. | 09-30-2010 |
20110098977 | HIGH SPEED CHIP SCREENING METHOD USING DELAY LOCKED LOOP - A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed. | 04-28-2011 |
20120114125 | AUDIO SIGNAL PROCESSING DEVICES HAVING POWER SIGNAL DECODING CIRCUITS THEREIN - An audio signal receiver includes left and right audio ports that are configured to receive left and right audio signals, respectively. The audio signal receiver also includes a power signal decoding circuit that is configured to extract a DC voltage from at least one of the left and right audio signals. Furthermore, the audio signal receiver includes an audio signal processor that is responsive to the left and right audio signals, and the audio signal processor is powered by the extracted DC voltage. | 05-10-2012 |
20120322712 | Stable Soap Based Cleansing System - Disclosed is a liquid soap composition which comprises:
| 12-20-2012 |
20130034505 | Cassia Derivatives - This invention related to a cationically and hydrophilically modified polygalactomannan having repeating units with an average D-mannosyl to D-galactosyl residue ratio of at least 5 to 1 and to compositions containing the same. A portion of the hydrogen atoms of hydroxyl groups situated on the mannosyl and galactosyl residues of the galactomannan are replaced with a hydrophilic and a cationic substituent. | 02-07-2013 |
20130129639 | Cassia Derivatives - This invention relates to a cationically and hydrophobically modified polygalactomannan having repeating units with a D-mannosyl to D-galactosyl residue ratio of at least 5 to 1 and to compositions containing same. A portion of the hydrogen atoms of hydroxyl groups situated on the mannosyl and galactosyl residues of the galactomannan are replaced with a hydrophobic substituent and a cationic substituent. | 05-23-2013 |
20140127149 | Cassia Derivatives - This invention relates to a cationically and amphiphilically modified polygalactomannan having repeating units with an average D-mannosyl to D-galactosyl residue ratio of at least 5 to 1 and to compositions containing same. A portion of the hydrogen atoms of hydroxyl groups situated on the mannosyl and galactosyl residues of the galactomannan are replaced with an amphiphilic and a cationic substituent. | 05-08-2014 |