Patent application number | Description | Published |
20080209372 | Estimation Of Process Variation Impact Of Slack In Multi-Corner Path-Based Static Timing Analysis - A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. | 08-28-2008 |
20080209373 | METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS - Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability. | 08-28-2008 |
20080209374 | Parameter Ordering For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion. | 08-28-2008 |
20080209375 | Variable Threshold System and Method For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. | 08-28-2008 |
20110055793 | TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN - An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks. | 03-03-2011 |
20130018617 | INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGNAANM Buck; Nathan C.AACI UnderhillAAST VTAACO USAAGP Buck; Nathan C. Underhill VT USAANM Dreibelbis; Brian M.AACI UnderhillAAST VTAACO USAAGP Dreibelbis; Brian M. Underhill VT USAANM Dubuque; John P.AACI JerichoAAST VTAACO USAAGP Dubuque; John P. Jericho VT USAANM Foreman; Eric A.AACI FairfaxAAST VTAACO USAAGP Foreman; Eric A. Fairfax VT USAANM Habitz; Peter A.AACI HinesburgAAST VTAACO USAAGP Habitz; Peter A. Hinesburg VT USAANM Hemmett; Jeffrey G.AACI St. GeorgeAAST VTAACO USAAGP Hemmett; Jeffrey G. St. George VT USAANM Venkateswaran; NatesanAACI Hopewell JunctionAAST NYAACO USAAGP Venkateswaran; Natesan Hopewell Junction NY USAANM Visweswariah; ChandramouliAACI Croton-on-HudsonAAST NYAACO USAAGP Visweswariah; Chandramouli Croton-on-Hudson NY USAANM Wang; XiaoyueAACI KanataAACO CAAAGP Wang; Xiaoyue Kanata CAAANM Zolotov; VladmimirAACI Putnam ValleyAAST NYAACO USAAGP Zolotov; Vladmimir Putnam Valley NY US - Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings. | 01-17-2013 |
20130036395 | EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS - Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset. | 02-07-2013 |
20130104092 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE - In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree. | 04-25-2013 |