Patent application number | Description | Published |
20090083593 | Test Method and Test Program of Semiconductor Logic Circuit Device - The number of output switching scan flip-flops in a capture operation is decreased, which decreases the capture power consumption, so that the reduction of the power supply voltage can be decreased to decrease generation of an erroneous test. For this purpose, 0 or 1 is filled in unspecified bits within a test cube to decrease the output switching scan flip-flops, to convert the test cube into a test vector with no unspecified bit X. In a combinational portion | 03-26-2009 |
20090259898 | Test vector generating method and test vector generating program of semiconductor logic circuit device - The X-type of each bit permutation is determined (step | 10-15-2009 |
20090319842 | GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM - Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device | 12-24-2009 |
20100064191 | DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device | 03-11-2010 |
20100205491 | LOGIC VALUE DETERMINATION METHOD AND LOGIC VALUE DETERMINATION PROGRAM - The provided are logic value determination method and program for identifying unspecified bits and determining their logic values shortly. The method enables to control the total number of logic value differences between corresponding input and output lines of combinational circuit. The method includes the first step for determining, when output has a logic value and input has an unspecified value, that the unspecified bit has the logic value of output, the second step for determining, when output has an unspecified value and input has a logic value, the logic value of the unspecified bit by justification, and the third step for calculating, when input and output both have unspecified values, probabilities of output to have 0 and 1, and determining the logic value of the unspecified bit based on the difference between the probabilities. The third step is repeated until the total number reaches a target value. | 08-12-2010 |
20100218063 | DON'T-CARE-BIT IDENTIFICATION METHOD AND DON'T-CARE-BIT IDENTIFICATION PROGRAM - The provided are a don't-care-bit identification method and program for identifying don't-care-bits from the first and the second input vectors in an input-vector pair while keeping the sensitization status of paths, in a combinational circuit, sensitized by applying the first and the second input vectors in serial to input lines of combinational circuit. The method identifies an unspecified bit from the first and the second input vectors V | 08-26-2010 |
20110140734 | GENERATING DEVICE, GENERATING METHOD, AND PROGRAM - Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design, by putting focus on internal lines in the circuit. The generation device includes a target internal line selection unit, a target internal line distinction unit, an identification unit that identifies a bit to be an unspecified bit and a bit to be a logic bit in the input bits, and an assignment unit that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits. The identification unit includes an unspecified bit identification unit and an input logic bit identification unit. | 06-16-2011 |
20110209024 | GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM - Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test. | 08-25-2011 |