| Patent application number | Description | Published |
|---|
| 20090091294 | Battery cell balancing systems using current regulators - According to one embodiment of the invention, there is provided a cell balancing circuit used for balancing a cell. The cell balancing circuit includes a bypass path coupled to the cell, a current regulator coupled to the bypass path, and a bleeding control switch. The current regulator is operable for producing a current and for controlling a conductance status of the bypass path. The bleeding control switch conducts the bypass path in response to the current produced by the current regulator. | 04-09-2009 |
| 20090096420 | Systems and methods for cell balancing - A cell balancing circuit comprises a first cell having a first voltage, a second cell in series with the first cell and having a second voltage that is greater than the first voltage, and a bypass path in parallel with the second cell for enabling a bypass current for the second cell if a difference between the first voltage and the second voltage is greater than a predetermined threshold. The bypass current is enabled for a balancing time period that is proportional to the difference between the fist voltage and the second voltage. | 04-16-2009 |
| 20100033128 | Circuit and method for cell balancing - According to one embodiment of the invention, there is provided a cell balancing circuit used for balancing a plurality of cells comprising a first cell and a second cell adjacent to the first cell. The cell balancing circuit includes a first shunt path coupled to the first cell in parallel for enabling a shunt current of the first cell, a second shunt path coupled to the second cell in parallel for enabling a shunt current of the second cell. The cell balancing circuit further includes a controller which is coupled to the first shunt path and the second shunt path. The controller is operable for alternately conducting the first shunt path and the second shunt path if the first cell and the second cell are unbalanced. | 02-11-2010 |
| 20110145629 | FLEXIBLE BUS ARCHITECTURE FOR MONITORING AND CONTROL OF BATTERY PACK - The present invention provides a control system which is used for a stacked battery of a plurality of battery packs. Each battery pack has a plurality of battery cells coupled in series. The control system is capable of reconfiguring communication among the battery packs in the stacked battery, and comprises a plurality of processors, a plurality of controllers, and a monitoring unit. The processors are coupled to the battery packs. Two adjacent processors among the processors are able to communicate with each other though a first bus. The controllers are coupled to the battery packs. Two adjacent controllers among the controllers are able to communicate with each other through a second bus. The processors are capable of communicating with the controllers through a third bus. The monitoring unit is used for monitoring communications among the plurality of processors and communications among the plurality of controllers. The monitoring unit is capable of detecting communication problems on the first bus and/or the second bus. The monitoring unit further is capable of reconfiguring communication paths among the plurality of processors and communication path among the plurality of controllers. | 06-16-2011 |
| 20110239053 | FLEXIBLE BUS ARCHITECTURE FOR MONITORING AND CONTROL OF BATTERY PACK - A method for diagnosing a control system for a stacked battery is disclosed. The control system comprises a plurality of processors, a plurality of controllers, and a monitoring unit (control unit). The method comprises sending a diagnostic information from the central unit to a top processor of the plurality of processors, transmitting a return information from the top processor of the plurality of processors to the central unit, comparing the diagnostic information sent from the central unit with the return information received by the central unit, and indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit. The steps are repeated by eliminating the top processor from a previous cycle and assigning a new top processor if there is no problem with the reconfigurable communication system. | 09-29-2011 |
| 20120303997 | Flexible Bus Architecture for Monitoring and Control of Battery Pack - A method for diagnosing a control system for a stacked battery. The control system comprises a plurality of processors, a plurality of controllers, and a monitoring unit (control unit). The method comprises sending a diagnostic information from the central unit to a top processor of the plurality of processors, transmitting a return information from the top processor of the plurality of processors to the central unit, comparing the diagnostic information sent from the central unit with the return information received by the central unit, and indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit. The steps are repeated by eliminating the top processor from a previous cycle and assigning a new top processor if there is no problem with the reconfigurable communication system. | 11-29-2012 |
| 20140203782 | BATTERY MANAGEMENT SYSTEM - A battery management system includes detecting circuitry and control circuitry coupled to the detecting circuitry. The detecting circuitry detects cell voltages of battery cells of a battery pack. The control circuitry alternates between a normal state and a charging prohibition state. In the normal state, charging of the battery cells is enabled and the cell voltages increase, and if a voltage of a battery cell of the battery cells exceeds a predetermined overcharge threshold, then the control circuitry transitions to the charging prohibition state. In the charging prohibition state, charging of the battery cells is disabled, and the voltage of the battery cell decreases if at least one cell of the battery cells has a voltage less than a balance threshold. If the voltage of the battery cell falls to a predetermined overcharge-released threshold, then the control circuitry transitions to the normal state and enables charging of the battery cells. | 07-24-2014 |
| 20150015209 | SYSTEM AND METHODS FOR CURRENT BALANCING - A battery module includes: a battery pack including multiple cells; control circuits corresponding to the cells, each control circuit including a control unit for managing the corresponding cell and a compensation unit for generating a corresponding compensation current such that the sum of the corresponding consumed current and the corresponding compensation current is equal to a target total current, where the control circuits include a first control circuit and a second control circuit, where the first control circuit includes a first control unit operating with a first consumed current, the second control circuit includes a second control unit operating with a second consumed current, and where the first control circuit conditionally generates a first compensation current and the second control circuit conditionally generates a second compensation current based on a comparison of the first consumed current and the second consumed current. | 01-15-2015 |
| Patent application number | Description | Published |
|---|
| 20100013100 | Method and System for Forming Conductive Bumping with Copper Interconnection - An integrated circuit system with one or more copper interconnects is provided. The one or more copper interconnects are in conductive contact with a substrate. The integrated circuit system includes a first dielectric layer, a copper material filling a first via through the first dielectric layer, a second dielectric layer in contact with the first dielectric layer, and a diffusion barrier layer. The diffusion barrier layer at least partially fills a second via through the second dielectric layer. At least a first part of the diffusion barrier layer is in direct contact with the copper material, and at least a second part of the diffusion barrier layer is in direct contact with the second dielectric layer. The integrated circuit system further includes a gold material at least partially filling the second via. The gold material is conductively connected with the copper material through the diffusion barrier layer and conductively connected with a substrate. Additionally, a method for making such an integrated circuit system with one or more copper interconnects is provided. | 01-21-2010 |
| 20110084327 | 3-D ELECTRICALLY PROGRAMMABLE AND ERASABLE SINGLE-TRANSISTOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate. | 04-14-2011 |
| 20110291190 | System and method for integrated circuits with cylindrical gate structures - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 12-01-2011 |
| 20120088363 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a gold material. The gold material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the gold material. Additionally, the method includes conductively connecting the gold material with the substrate. | 04-12-2012 |
| 20130029483 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material. | 01-31-2013 |
| 20130102116 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop. | 04-25-2013 |
| 20130228833 | SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES - A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration. | 09-05-2013 |
| 20130302951 | SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE - A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode. | 11-14-2013 |
| 20140193956 | TRANSISTOR AND FABRIATION METHOD - Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer. | 07-10-2014 |
| 20140203243 | THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR AND FABRICATION METHOD - Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain. | 07-24-2014 |
| 20140353715 | FINFET DEVICE AND FABRICATION METHOD THEREOF - A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member. The transistor device may further include a fin bar. The fin bar may be formed of a first semiconductor material, may be disposed between the source member and the drain member, and may overlap the well portion. The transistor device may further include a fin layer. The fin layer may be formed of a second semiconductor material, may be disposed between the source member and the drain member, and may contact the fin bar. | 12-04-2014 |
| 20150024559 | SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 01-22-2015 |
| 20150034905 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device is provided. The method includes forming a substrate structure, wherein the substrate structure includes a substrate and a fin-shaped barrier layer formed on a surface of the substrate; forming a quantum well (QW) material layer on a surface of the fin-shaped barrier layer; and forming a barrier material layer on the QW material layer. | 02-05-2015 |
| 20150034906 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved. | 02-05-2015 |
| 20150129926 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined. | 05-14-2015 |
| 20150214302 | THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR - Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain. | 07-30-2015 |
| Patent application number | Description | Published |
|---|
| 20100137660 | PROCESS FOR THE CRYSTALLIZATION SEPARATION OF P-XYLENE - Provided is a process for crystallization separating p-xylene, comprising: a) feeding a mixed xylenes stream comprising greater than or equal to 60% by weight, of p-xylene, such as 60% to 98% by weight of p-xylene, to a crystallization unit to perform cooling crystallization, to obtain a slurry comprising p-xylene crystals; and b) feeding the slurry to a filtration and purification unit, to obtain a mother liquor, washings, and p-xylene, wherein the filtration and purification unit uses a simulated moving bed or a combination of multiple moving beds. | 06-03-2010 |
| 20100228066 | Integrated Process for the Production of P-Xylene - The present invention provides an integrated process for the production of p-xylene, comprising the steps of A) separating a mixed feedstock containing benzene, toluene, C | 09-09-2010 |
| 20130284584 | PROCESS FOR SEPARATING ETHYLENE GLYCOL AND 1, 2-BUTANEDIOL - The present invention relates to a process for separating ethylene glycol and 1,2-butanediol. A material flow containing ethylene glycol and 1,2-butanediol gets into the lower-middle part of the azeotropic rectification column C | 10-31-2013 |
| Patent application number | Description | Published |
|---|
| 20100309086 | MULTIPLE-INPUT MULTIPLE-OUTPUT DEVICE - A multiple-input multiple-output (MIMO) device includes a substrate, a shielding cover and a MIMO antenna. The shielding cover is positioned on the substrate, and includes a plurality of sidewalls. The MIMO antenna includes a first solid antenna, a second solid antenna, and a plane antenna. The first solid antenna and the second solid antenna are electrically connected to two ends of one sidewall of the shielding cover, respectively. The first plane antenna is configured on the substrate, and disposed between the first solid antenna and the second solid antenna. | 12-09-2010 |
| 20130135174 | ELECTRONIC DEVICE EMPLOYING MULTIFUNTION ANTENNA ASSEMBLY - An electronic device defines a receiving groove for an antenna, a first opening, and a second opening. The first opening and the second opening are at two opposite ends of the receiving groove, and allow an antenna assembly to be extended or retracted in the receiving groove to allow the electronic device to receive different types of wireless signals. | 05-30-2013 |
| 20140340028 | CHARGER WITH HUB - A charger includes an enclosure, a charging circuit received in the enclosure., a latching member and a pair of elastic members. The enclosure defines a matching groove. The pair of elastic members are electrically connected to the charging circuit and are mounted on opposite sidewalls of the matching groove. The latching member is mounted in the matching groove, and is flexible. The present disclosure further provides a hub matching with the charger. The hub includes a main body, a circuit unit, a bulge and a pair of conductive pieces. The main body defines a receiving groove. The bulge protrudes from a bottom of the receiving groove. The pair of conductive pieces are electrically connected to the circuit unit and are located at opposite sidewalls of the bulge. A sidewall of the bulge defines a latching hole, and the latching member latches with an edge of the hole. | 11-20-2014 |
| 20140340029 | CHARGER WITH HUB - A charger includes a charging unit and a hub unit. The charging unit includes an enclosure, a charging circuit and two wires. The enclosure defines a matching groove. Opposite sidewalls of the matching groove separately define a limiting groove. The hub unit includes a foundation, a circuit unit, a locking protrusion, a pair of bolts and a pair of hook assemblies. The foundation defines a holder. The locking protrusion, the bolts and the latching members are all received in the holder. One end of each of the two wires is electrically coupled to the charging circuit, and the other end of each of the two wires extends through the matching groove and the receiving groove in that order and electrically couples to the circuit unit. | 11-20-2014 |
| 20150037615 | ELECTRONIC DEVICE AND POLARITY-SAFE STRUCTURE CONFIGURED TO RECEIVE A BATTERY - An electronic device ensuring the polarity-correct installation of a battery includes a polarity-safe structure. The polarity-safe structure includes a fixing member located in a fixing groove and an elastic member secured in a receiving groove opposite to the fixing member. The battery cathode can be electrically coupled to the elastic member, but while the battery anode can be coupled to the fixing member, it cannot couple to the elastic member. | 02-05-2015 |
| Patent application number | Description | Published |
|---|
| 20090137857 | METHOD FOR PREPARATION OF ETHYLENE AND PROPYLENE BY CATALYTIC CRACKING USING A FLUID-BED CATALYST - A method for preparation of ethylene and propylene by catalytic cracking using a fluid-bed catalyst. The main technical problems to be solved are a relatively high reaction temperature, and low activities and poor selectivities of the catalyst at a low temperature, during the reaction for preparing ethylene and propylene by catalytically cracking naphtha. The fluid-bed catalyst is a composition of the chemical formula Mo | 05-28-2009 |
| 20090288990 | Catalyst for Catalytic Cracking Fluidized Bed - The present invention relates to a catalyst for catalytic cracking fluidized-bed, and the technical problems to be primarily solved by the present invention are high reaction temperature, low cryogenic activity of catalysts and worse selectivity during the preparation of ethylene-propylene by catalytically cracking naphtha. The present invention uses the composition having the chemical formula (on the basis of the atom ratio): A | 11-26-2009 |
| 20130225397 | Binderless Molecular Sieve Catalyst and a Preparation Method Thereof - The present invention relate to a binderless molecular sieve catalyst and a process for preparing the same, which are mainly useful for solving the problems of the current catalysts, such as lower activity, less pore volume and worse diffusivity. The present invention relates to a novel binderless molecular sieve catalyst, comprising, based on the weight of the catalyst, 90-100 wt. % of a molecular sieve, 0-10 wt. % of a binder, and 0-10 wt. % of an anti-wear agent, wherein said catalyst has a pore volume of 0.1-0.5 ml/g, an average pore diameter of 50-100 nm, and a porosity of 20-40%; the anti-wear agent is selected from the rod or needle-like inorganic materials having a length/diameter ratio of 2-20. Said catalyst has the advantages of higher activity, greater pore volume, larger average pore diameter and porosity, and better diffusivity, and well solves said problems and can be used for the industrial preparation of binderless molecular sieve catalysts. | 08-29-2013 |
| Patent application number | Description | Published |
|---|
| 20140038115 | Dense/Dilute Pulverized Coal Separator Structure of Single-fireball Octagonal Direct-flow Burner - The invention discloses a dense/dilute pulverized coal separator structure of a single-fireball octagonal direct-flow burner, of which a boiler body is provided with eight burner groups, each water cooled wall is provided with two burner groups respectively, each of the burner groups comprises multiple nozzles toward the same burner, and center lines of all nozzles on the eight burner groups form an imaginary tangent circle in a furnace along the same tangential direction. In the dense/dilute pulverized coal separator structure, eight burner groups are arranged on four water cooled walls of the boiler, thus increasing pulverized coal concentration of a pulverized rich coal area, allowing wall heat load qHr of a lower burner area to be higher, allowing burning temperature of the area to meet requirements for anthracite burning stability, shortening distance of jet flow from a nozzle outlet to downstream adjacent air flow, being capable of using lower primary pulverized coal air flow velocity, enhancing heat flow intensity at the nozzle outlet, improving convection and radiation heat transfer capacity, and ensuring timely ignition of pulverized anthracite air flow and stable burning of the boiler at low load without oil. | 02-06-2014 |
| 20150291593 | NOVEL HETEROARYL AND HETEROCYCLE COMPOUNDS, COMPOSITIONS AND METHODS - Provided are novel heteroaryl and heterocycle compounds of formula (I-1), (I-2) or (I-3) and pharmaceutical compositions comprising them, uses and methods thereof for inhibiting the activity of PI | 10-15-2015 |
| 20150307520 | NOVEL HETEROARYL AND HETEROCYCLE COMPOUNDS, COMPOSITIONS AND METHODS THEREOF - Disclosed are novel heteroaryl and heterocycle compounds of formula I-1, I-2 or I-3 and pharmaceutical compositions comprising them, uses and methods thereof for inhibiting the activity of PI | 10-29-2015 |
| Patent application number | Description | Published |
|---|
| 20090211887 | MOVING CONTACT HEAD FOR TAP SWITCHES - A moving contact head for tap switches comprises a moving contact head installation plate component ( | 08-27-2009 |
| 20090211890 | EXTERNAL HANGING COMBINED VACUUM ON-LOAD TAP SWITCH - The invention relates to an external hanging combined vacuum on-load tap switch, comprising a case, a tap selector, a switching means assembly, a transmission device, and one electric operation mechanism, wherein one lateral side wall of the case is provided with a connecting terminal connected with the coil tap of a transformer; the external side of the wall is provided with a first flange plate and is connected with a second flange plate of the transformer; the tap selector and the switching means assembly are arranged inside the case in parallel; and the electric operation mechanism is connected with the transmission device and drives the tap selector and the switching means assembly to achieve tapping and switching through the transmission device. | 08-27-2009 |
| 20140291130 | EXTERNAL ON-LOAD TAP CHANGER - Disclosed is a suspensible external combined on-load tap changer, including: a switch box, a switch body and a motor mechanism, a top box wall of the switch box being opened with a top opening, a top box cover being mounted on the top opening, wherein the switch body is detachably mounted in the switch box and is entirely lifted in and lifted out by the top opening; and the motor mechanism is connected with the switch body in a driving manner. The switch body in the present invention uses a hoisting structure, and the top box wall of the switch box is opened with a top opening with a size large enough, so that the switch body is directly lifted in and lifted out of the switch box from the top opening, and installation and maintenance are easier. | 10-02-2014 |
| Patent application number | Description | Published |
|---|
| 20110006304 | SEMICONDUCTOR DEVICE WITH ALTERNATELY ARRANGED P-TYPE AND N-TYPE THIN SEMICONDUCTOR LAYERS AND METHOD FOR MANUFACTURING THE SAME - The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased. | 01-13-2011 |
| 20110241110 | TERMINAL STRUCTURE FOR SUPERJUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME - A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed. | 10-06-2011 |
| 20110241156 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Methods for manufacturing a semiconductor device with alternating P type and N type semiconductor conductive regions are disclosed. One method includes forming a trench in an N type epitaxial layer; forming carbon-contained silicon layer on sidewalls of the trench; and filling the trench with P type semiconductor layer. In another method, the carbon-contained silicon layer is replaced by a carbon film formed by diffusion process. The carbon-contained silicon layer or the carbon film can effectively inhibit the diffusion of P type impurities into the N type semiconductor layers. Further, a semiconductor device having carbon-contained layer or carbon film formed between P type and N type conductive layers is also disclosed. | 10-06-2011 |
| 20110287613 | MANUFACTURING METHOD OF SUPERJUNCTION STRUCTURE - A manufacturing method of superjunction structure is disclosed. After the growth of an epitaxial layer on a substrate, deep trenches are etched in the epitaxial layer. A mixture of silicon source gas, hydrogen gas, halide gas and doping gas is used for trench tilling by means of epitaxial growth. The epitaxial growth rate on trench sidewalls near the bottom of the trench is set to be higher than that near the top of the trench by adjusting the flow rates of the silicon source gas and the halide gas and other parameters. By changing the flow rate of the doping gas at different stages of the epitaxial filling process, the trenches can be filled with epitaxial layers of different doping concentrations, with higher doping concentration near the bottom and lower doping concentration near the top. | 11-24-2011 |
| 20110306189 | METHOD FOR ETCHING AND FILLING DEEP TRENCHES - A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer. | 12-15-2011 |
| 20110316121 | METHOD FOR MANUFACTURING TRENCH TYPE SUPERJUNCTION DEVICE AND TRENCH TYPE SUPERJUNCTION DEVICE - A method for manufacturing trench type super junction device is disclosed. The method includes the step of forming one or more P type implantation regions in the N type epitaxial layer below the bottom of each trench. By using this method, a super junction device having alternating P type and N type regions is produced, wherein the P type region is formed by P type silicon filled in the trench and P type implantation regions below the trench. The present invention can greatly improve the breakdown voltage of a super junction MOSFET. | 12-29-2011 |
| 20120326226 | SUPERJUNCTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device. | 12-27-2012 |
| 20130082323 | SUPERJUNCTION STRUCTURE, SUPERJUNCTION MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - A superjunction structure with unevenly doped P-type pillars ( | 04-04-2013 |
| 20130105796 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD | 05-02-2013 |
| 20130130486 | METHOD OF FORMING SILICIDE LAYERS - A method of forming silicide layers is disclosed, the method including: providing a silicon substrate which includes at least one first region and at least one second region; depositing a dielectric layer over the silicon substrate; forming at least one opening having a great width/depth ratio in the dielectric layer above the at least one first region, and forming at least one opening having a small width/depth ratio in the dielectric layer above the at least one second region; depositing a metal and performing a high-temperature annealing to form a thick silicide layer in each of the at least one opening above each of the at least one first region and to form a thin silicide layer in each of the at least one opening above each of the at least one second region; removing the remaining metal not formed into the silicide layers. | 05-23-2013 |
| 20130234201 | FIELD STOP STRUCTURE, REVERSE CONDUCTING IGBT SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THE SAME - A field stop structure is disclosed. The field stop structure is divided into a three-dimensional structure by a plurality of trenches formed on a back side of a silicon substrate and hence obtains a greater formation depth in the substrate and can achieve a higher ion activation efficiency. Moreover, a first electrode region of a fast recovered diode (FRD) is formed in the trenches, thereby enabling the integration of a FRD with an insulated gate bipolar transistor (IGBT) device. Methods for forming field stop structure and reverse conducting IGBT semiconductor device are also disclosed. | 09-12-2013 |
| 20140042522 | RF LDMOS DEVICE AND FABRICATION METHOD THEREOF - A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate, a p-type epitaxial layer, a p-type well, a lightly doped n-type drain region, a gate oxide layer, a polysilicon gate, a dielectric layer and a Faraday shield. The Faraday shield includes: a horizontal portion covering a portion of the polysilicon gate and isolated from the polysilicon gate by the dielectric layer; a step-like portion with at least two steps covering a portion of the lightly doped n-type drain region and isolated from the lightly doped n-type drain region by the dielectric layer; and a vertical portion connecting the horizontal portion with the step-like portion and isolated from the polysilicon gate and the lightly doped n-type drain region by the dielectric layer. A method of fabricating such an RF LDMOS device is also disclosed. | 02-13-2014 |
| 20140048878 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a P+ substrate; a P− epitaxial layer over the P+ substrate; a P-well and an N− drift region in the P− epitaxial layer and laterally adjacent to each other; an N+ source region in the P-well and connected to a front-side metal via a first contact electrode; an N+ drain region in the N− drift region and connected to the front-side metal via a second contact electrode; a gate structure on the P− epitaxial layer and connected to the front-side metal via a third contact electrode; and a metal plug through the P− epitaxial layer and having one end in contact with the P+ substrate and the other end connected to the front-side metal, the metal plug being adjacent to one side of the N+ source region that is farther from the N− drift region. A method for fabricating the semiconductor device is also disclosed. | 02-20-2014 |
| 20140061783 | SUPER-JUNCTION DEVICE AND METHOD OF FORMING THE SAME - A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed. | 03-06-2014 |
| Patent application number | Description | Published |
|---|
| 20120284421 | PICTURE IN PICTURE FOR MOBILE TV - The invention discloses a method, a terminal and a media server for supporting Picture in Picture (PiP) in a communication network. The method comprises sending to a media server ( | 11-08-2012 |
| 20140010090 | BROADCASTING OF DATA FILES AND FILE REPAIR PROCEDURE WITH REGARDS TO THE BROADCASTED DATA FILES - A method in a Broadcast Multicast Service Centre, BM-SC, comprising at least two file repair servers is arranged for performing a file repair session following a broadcast transmission of a data file to a User Equipment, UE, in a radio communication system. After having determined whether a first of the file repair servers is experiencing, or is predicted to experience, an overload condition, an information message, indicating the existing or predicted overload experience of the first file repair server and capable of indicating a time interval, T, which shall have elapsed before the UE is allowed to transmit a file repair request to the first file repair server, is transmitted to the UE in case it is determined that the first file repair server is experiencing, or is predicted to experience, an overload condition. | 01-09-2014 |
| 20140321556 | REDUCING AMOUNT OF DATA IN VIDEO ENCODING - A method for encoding screen outputs of an application to a series of video sequences, in which each video sequence can comprise an intra-frame (I-frame) and inter-frames (P-frames) relating to the I-frame, and each video sequence is formed for one screen output. The method can comprise forming a first video sequence for a first screen output, wherein the first video sequence can include an I-frame and (p-frames), and forming a second video sequence including an I-frame and (P-frames) for a second screen output, wherein the I-frame of the second video sequence can be obtained by encoding a changed area of the second screen output compared to the first screen output. A device for encoding, encoder, a device for decoding, and a decoding are also provided. The video data can be reduced according to the present invention. | 10-30-2014 |
| 20150189544 | Method and Arrangement For Distributing Information During Broadcast Delivery - A BM-SC, and a method therein for transmitting data file by broadcast session to at least one UE, in a radio communication system; and a UE and a method therein for receiving a broadcast session of transmission of a data file from a BM-SC are provided. The method in the BM-SC comprises determining to transmit the data file to the at least one UE, and determining a FEC redundancy level to use for the transmission. The method also comprises transmitting, to the at least one UE, the data file using the determined FEC redundancy level and an indication of the determined FEC redundancy level. | 07-02-2015 |
| 20150278022 | METHODS AND ARRANGEMENTS FOR HANDLING FILE REPAIR DURING MBMS OR eMBMS DELIVERY - Methods for delivering user information via Multimedia Broadcast Multicast Services (MBMS) or enhanced Multimedia Broadcast Multicast Services (eMBMS) to user equipments capable of receiving this user information are disclosed. A method provides a file repair size threshold which indicates a maximum allowed file repair size to the user equipments. Another method is executable in a user equipment for determining whether or not to execute a fire repair request on the basis of a comparison of a required file repair and a file repair size threshold in case a file repair size threshold is available at the user equipment. Related user equipment and apparatuses capable of executing the methods are also disclosed. | 10-01-2015 |
| Patent application number | Description | Published |
|---|
| 20110222728 | Method and Apparatus for Scaling an Image in Segments - A method and an apparatus for scaling an image in segments are disclosed. The method includes: identifying scene features in each input video frame, and obtaining information about distribution of multiple features in the video frame; obtaining multiple feature distribution areas corresponding to the information about distribution of the multiple features, and obtaining multiple scale coefficients; and scaling the corresponding multiple feature distribution areas in each video frame according to the multiple scale coefficients. | 09-15-2011 |
| 20130290754 | LOAD MONITORING APPARATUS AND METHOD - Embodiments of the present invention provide a load monitoring apparatus and method. The apparatus includes: an operation unit, configured to determine indication information for indicating a working state of each processing module in the operation unit; a working state unit, configured to receive the indication information from the operation unit, and determine load amount information in a current monitoring period according to the indication information, where the load amount information is used for indicating a load amount state of the operation unit in the current monitoring period; and a load monitoring unit, configured to receive the load amount information from the working state unit and record the load amount information, and send the load amount information to a system controller, so that the system controller adjusts a working frequency of the operation unit according to the load amount information. | 10-31-2013 |
| 20130300769 | IMAGE ROTATION CONTROL METHOD AND DEVICE - Embodiments of the present invention disclose an image rotation control method and device. The method includes: reading image blocks of a first image from a first buffer according to a rotation angle, where the first image is in a first image format; writing the read image blocks into a preset second buffer; and reading image data from the second buffer according to a second image format, so as to obtain a rotated second image. | 11-14-2013 |
| Patent application number | Description | Published |
|---|
| 20090031295 | Method and System for Customizing a Software Application - The technique introduced here includes a uniform customization system, which can support the customization of multiple software applications simultaneously. Customization data of a software application can be developed separately from the development of the application. The customization data is then stored, via the uniform customization system, into a customization storage. When the software application is executed, the software application retrieves, from the storage, the values of the customization data via the uniform customization system. The uniform customization system outputs the retrieved customization data indicating the current working context of a user, which may be used by the user to locate customization options in a customization user interface of the software application, for customizing functions performed in the current working context. | 01-29-2009 |
| 20100031233 | EXTENDED ENTERPRISE CONNECTOR FRAMEWORK USING DIRECT WEB REMOTING (DWR) - Techniques for extended enterprise connector framework are described herein. According to one embodiment, a Java proxy is generated in a form of Java beans at a Web server as a mid-layer, using an enterprise connector. The enterprise connector provides object oriented classes that encapsulate specific function calls of a Java connector which represents a set of proprietary APIs (application programming interfaces) to access RFC modules of a backend enterprise system. A JavaScript proxy is generated for a frontend client that communicates with the Web server over the Web using a DWR (direct Web remoting) mechanism to allow the JavaScript proxy to directly access the Java proxy of the mid-layer via an AJAX (asynchronous Java and extensible markup language or XML) communication mechanism, where the JavaScript is invoked by a Web application of the frontend client at runtime. Other methods and apparatuses are also described. | 02-04-2010 |
| 20120278794 | METHOD AND SYSTEM FOR CUSTOMIZING A SOFTWARE APPLICATION - The technique introduced here includes a uniform customization system, which can support the customization of multiple software applications simultaneously. Customization data of a software application can be developed separately from the development of the application. The customization data is then stored, via the uniform customization system, into a customization storage. When the software application is executed, the software application retrieves, from the storage, the values of the customization data via the uniform customization system. The uniform customization system outputs the retrieved customization data indicating the current working context of a user, which may be used by the user to locate customization options in a customization user interface of the software application, for customizing functions performed in the current working context. | 11-01-2012 |
