Patent application number | Description | Published |
20130271073 | COIL TECHNIQUES - Techniques are disclosed involving coils that may be used to exchange wireless energy between devices. For instance, a device may include a coil having a plurality of turns arranged along an arc. Further, the coil may have first and second ends that are substantially normal to the arc. The coil may be arranged within a casing of the device. This casing may have first and second non-parallel surfaces. In embodiments, the first end of the coil may be directed to (be substantially parallel with and proximate to) the first surface, while the second end of the coil may be directed to the substantially parallel with and proximate to) the second surface. The coil may be employed in wireless power transfer and/or near field communication applications. | 10-17-2013 |
20140065956 | NEAR FIELD COUPLING SOLUTIONS FOR WI-FI BASED WIRELESS DOCKING - Described herein are techniques related one or more systems, apparatuses, methods, etc. for a wireless fidelity (Wi-Fi) based wireless docking in an enterprise environment. In an implementation, a separate low radiating antenna is constructed and installed at a bottom surface of a wireless device and at a docking surface of a docking station. In this implementation, the low radiating antenna is configured to provide local wireless communication (i.e., Wi-Fi based communication) between a docking pair that includes the wireless device and the docking station. | 03-06-2014 |
20140092543 | KEYBOARD INTEGRATED NFC ANTENNA - A metal baseboard with a planar shape which is placed close to a Near Field Communication (NFC) radio antenna may be configured with a number of slots in the metal. These slots may disrupt the eddy current that would otherwise be induced in the metal by magnetic emissions emanating from the NFC antenna. The reduction in eddy current that results from these slots may reduce the severe attenuation of the signal that would otherwise be caused by the metal. In general, each slot may run approximately perpendicular to the direction of the expected eddy current. This may be approximated by having many of the slots each run perpendicular to the nearest part of the antenna wiring. | 04-03-2014 |
20140346886 | ANTENNA CONFIGURATION TO FACILITATE NEAR FIELD COUPLING - Described herein are techniques related to near field coupling and wireless power transfers. A portable device may include a coil antenna that includes an upper loop and a lower loop to form a figure-eight arrangement. The figure-eight coil antenna arrangement is wrapped against top and bottom surfaces of a component to establish near field coupling through front side, top side, bottom side, or corner side of the portable device. Further, a flux guide may be placed between the coil antenna and the component to facilitate magnetic flux at the upper loop and the lower loop to induce current of the same phase during receive mode. During transmit mode, the flux guide facilitates the magnetic flux at the upper loop and the lower loop to generate magnetic fields of the same direction. | 11-27-2014 |
20140362837 | ANTENNA COUPLER FOR NEAR FIELD WIRELESS DOCKING - Described herein are techniques related to one or more systems, apparatuses, methods, etc. for a wireless fidelity (Wi-Fi) based wireless docking station arrangement. | 12-11-2014 |
20150035474 | INTEGRATION OF WIRELESS CHARGING UNIT IN A WIRELESS DEVICE - Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a wireless charging and a wireless connectivity in a device. | 02-05-2015 |
Patent application number | Description | Published |
20090268683 | PARTIAL RADIO LINK CONTROL STATUS REPORT - Systems and methodologies are described that facilitate formation and/or dispatch of radio link control (RLC) protocol status reports to a base station. The system can include components that quantify an absence of protocol data units, ascertain whether a number of absent protocol data units exceeds the size of a transmission side grant, insert a sequence number associated with a first absent protocol data unit into an acknowledgement sequence number field associated with a partial status report, incorporates the sequence number associated with the first absent protocol data unit in the partial status report, includes sequence numbers of subsequent absent protocol data units into the partial status report without exceeding the transmission side grant, and sends the partial status report to the base station. | 10-29-2009 |
20100034095 | PROCESSING POLLING REQUESTS FROM RADIO LINK CONTROL PEERS - This innovation relates to systems and methods for transmission of protocol data units, and more particularly to processing polling requests from a radio link control peer. A radio link control transmitter can poll a receiver to obtain a report regarding the status of a set of data packets, and the polls can be sent in-band with a data packet. The receiver can determine to wait before sending the status report based on one or more characteristics of the received data packets. | 02-11-2010 |
20100034187 | EFFICIENT PACKET HANDLING FOR TIMER-BASED DISCARD IN A WIRELESS COMMUNICATION SYSTEM - Systems and methodologies are described herein that facilitate efficient handling of packets (e.g., Packet Data Convergence Protocol (PDCP) Protocol Data Units (PDUs) or Service Data Units (SDUs)) in a wireless communication system. As described herein, a number of consecutive packets that are discarded due to a discard timer expiration event and/or other causes can be monitored and compared to a number of tolerated consecutive discarded packets. If the number of consecutive discarded packets does not exceed the number of tolerated consecutive packets, conventional processing operations such as header modification and compression, ciphering, or the like can be omitted for respective packets subsequent to a discarded packet, thereby significantly reducing processing overhead. As further described herein, the number of tolerated consecutive discarded packets can be chosen to maintain header compression (e.g., Robust Header Compression (RoHC)) synchronization, ciphering synchronization, and/or other suitable properties. | 02-11-2010 |
20100118892 | EFFICIENT UE QOS/UL PACKET BUILD IN LTE - An apparatus for wireless communication includes a processing system. The processing system is configured to perform a first set of functions in a first thread. The first set of functions includes obtaining second data from a second thread and providing first data to the second thread to facilitate construction of an uplink packet in the second thread. The processing system is further configured to perform a second set of functions in the second thread. The second set of functions includes obtaining the first data, constructing the uplink packet based on the first data, and providing the second data to the first thread to facilitate the performing of the first set of functions. | 05-13-2010 |
20120176898 | DOWNLINK FLOW CONTROL USING PACKET DROPPING TO CONTROL TRANSMISSION CONTROL PROTOCOL (TCP) LAYER THROUGHPUT - Certain aspects of the present disclosure relate to wireless communications and methods and apparatus for downlink flow control at a user equipment (UE). Aspects generally include monitoring, by a UE, one or more parameters related to the UE, and selectively dropping received packets based on the one or more parameters in order to trigger a rate control mechanism. Selectively dropping received packets may occur at a Packet Data Convergence Protocol (PDCP) layer in order to reduce a corresponding transmission control protocol (TCP) throughput. Accordingly, packets may be selectively dropped prior to reaching an applications processor. | 07-12-2012 |
Patent application number | Description | Published |
20110296064 | UPLINK DATA THROTTLING BY BUFFER STATUS REPORT (BSR) SCALING - A technique for uplink data throttling includes buffer status report (BSR) scaling. A target data flow rate may be determined based on at least on condition of a wireless device. The buffer status report may be adjusted to cause the target flow rate and transmitted by the wireless device. The wireless device may then receive a flow control command based on the buffer status report. | 12-01-2011 |
20120039176 | METHODS AND SYSTEMS FOR DOWNLINK FLOW CONTROL IN A WIRELESS COMMUNICATION SYSTEM - Methods and apparatus for downlink rate control by a user equipment (UE) (e.g., when an overload condition happens at the UE) are provided. For example, the UE may experience CPU overload, CPU near-overload, memory overload, memory near-overload, overheating or near-overheating. For certain aspects, the UE may simulate a “degraded channel” in order to cause an eNodeB to lower a transmission rate or block-size as it would in response to receiving an indication of bad channel conditions. The UE may simulate a degraded channel by modifying a channel quality indicator (CQI) and transmitting negative acknowledgment (NACK) messages to the eNodeB. Therefore, the eNodeB may be responsible for guaranteeing quality of service (QoS) based on the new degraded channel condition. In other aspects, UE downlink flow control is achieved by dropping hybrid automatic repeat request (HARM) packets or reducing a radio link control (RLC) receive window size when an overload condition occurs. | 02-16-2012 |
20130039173 | METHODS AND APPARATUS FOR OVERLOAD MITIGATION USING UPLINK TRANSMIT POWER BACKOFF - Certain aspects of the disclosure relate generally to uplink flow control of wireless devices for mitigation of overload issues. A user equipment (UE) may reduce an average transmit power for the uplink channel based on whether an overload metric (e.g., temperature metric) exceeds a threshold value. The UE may perform duty cycling for an uplink control channel when an overactive uplink control channel is a dominating factor in a thermal issue. The UE may further reduce a maximum power transmit limit (MTPL) for one or more uplink channels, such as physical uplink control channel (PUCCH) and physical uplink shared channel (PUSCH). | 02-14-2013 |
20140133410 | METHODS AND APPARATUS FOR LTE MAC LOGICAL CHANNEL PRIORITIZATION BASED ON CONTROL DATA - Aspects of the present disclosure provide methods, systems, devices and/or apparatuses for logical channel prioritization by a user equipment (UE) within a Long Term Evolution (LTE) wireless communications network. The UE may have multiple logical channels each associated with one or more applications or services of the UE. The UE may identify whether a quality of service (QoS) obligation to allocate at least a portion of uplink resources to a logical channel for a time period is present, and may also identify whether the logical channel has control data to be transmitted from the UE. If a QoS obligation and/or control data are present for the logical channel, the UE may allocate at least a portion of the uplink resources to the logical channel. | 05-15-2014 |
Patent application number | Description | Published |
20090261899 | Amplifier with Automatic Gain Profile Control and Calibration - Embodiments of the present invention provide systems and methods for automatic amplifier gain profile control, including a method for automatically configuring a variable gain profile amplifier according to received input and a variable gain profile amplification system. Further, embodiments of the present invention provide systems and methods for increased gain profile accuracy, including methods and systems to reduce the effects of temperature and/or process variations on the gain profile of an amplifier. | 10-22-2009 |
20100197244 | Direct coupled radio frequency (RF) transceiver front end - A method and apparatus is disclosed to couple a transmission amplifier and a reception amplifier to a shared medium. An output of the transmission amplifier is directly coupled to an input of the reception amplifier to form a common connection. The transmission amplifier and the reception amplifier may receive a first amplifier bias via the common connection. In response to the first amplifier bias, the transmission amplifier provides a first communication signal to the shared medium and the reception amplifier does not provide a second communication signal from the shared medium. Alternatively, the transmission amplifier and the reception may receive a second amplifier bias via the common connection. In response to the second amplifier bias, the reception amplifier provides the second communication signal from the shared medium and the transmission amplifier does not provide the first communication signal to the shared medium. | 08-05-2010 |
20100308918 | Amplifier with Automatic Gain Profile Control and Calibration - Embodiments of the present invention provide systems and methods for automatic amplifier gain profile control, including a method for automatically configuring a variable gain profile amplifier according to received input and a variable gain profile amplification system. Further, embodiments of the present invention provide systems and methods for increased gain profile accuracy, including methods and systems to reduce the effects of temperature and/or process variations on the gain profile of an amplifier. | 12-09-2010 |
20110298542 | Amplifier with Automatic Gain Profile Control and Calibration - Embodiments of the present invention provide systems and methods for automatic amplifier gain profile control, including a method for automatically configuring a variable gain profile amplifier according to received input and a variable gain profile amplification system. Further, embodiments of the present invention provide systems and methods for increased gain profile accuracy, including methods and systems to reduce the effects of temperature and/or process variations on the gain profile of an amplifier. | 12-08-2011 |
20130084816 | Wideband Power Efficient High Transmission Power Radio Frequency (RF) Transmitter - Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated. In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies. | 04-04-2013 |
20130235953 | Wideband Power Efficient High Transmission Power Radio Frequency (RF) Transmitter - Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated, In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies. | 09-12-2013 |
Patent application number | Description | Published |
20120229211 | AMPLIFIER USING FAST DISCHARGING REFERENCE - Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier. | 09-13-2012 |
20120229212 | AMPLIFIER USING MASTER-SLAVE CONTROL SCHEME - Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received. | 09-13-2012 |
20120249099 | BOOT-STRAP REGULATOR FOR GATE DRIVER - Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage. | 10-04-2012 |
Patent application number | Description | Published |
20090251190 | SYSTEM AND METHOD FOR GENERATING TWO EFFECTIVE FREQUENCIES USING A SINGLE CLOCK - A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal. | 10-08-2009 |
20100241923 | Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding - Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding. An LDPC code is concatenated with a RS code or a binary product code (e.g., using row and column encoding of matrix formatted bits) thereby generating coded bits for use in generating a signal that is suitable to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. and various implementations of cyclic redundancy check (CRC) may accompany the product coding and/or additional ECC/FEC employed. The redundancy of such coded signals as generated using the principles herein are in the range of approximately 20% thereby providing a significant amount of redundancy and a high coding gain. Soft decision decoding may be performed on such coded signal generated herein. | 09-23-2010 |
20100241925 | Forward Error Correction (FEC) scheme for communications - Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing. | 09-23-2010 |
20100241926 | Communication device employing binary product coding with selective additional Cyclic Redundancy Check (CRC) therein - Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions. | 09-23-2010 |
20110052216 | Electronic dispersion compensation within optical communications using reconstruction - Electronic dispersion compensation within optical communications using reconstruction. Within a communication system that includes any optical network portion, segment, or communication link, etc., that optical component/portion of the communication system is emulated within the electronic domain. For example, in a communication device having receiver functionality, deficiencies that may be incurred by the at least one optical portion of the communication system are compensated in the electronic domain of the communication device having the receiver functionality by employing reconstruction logic and/or circuitry therein. Multiple decision feedback equalizers (DFE) circuitries, implemented in the electronic domain, may be employed to provide feedback from different portions of the receiver functionality in accordance with performing compensation of optical incurred deficiencies (e.g., dispersion, non-linearity, inter-symbol interference (ISI), etc.). Within a communication device's receiver portion, equalization and compensation is performed in the electronic domain as adapted for high speed applications and higher order modulation schemes. | 03-03-2011 |
20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 01-12-2012 |
20120179949 | METHOD AND SYSTEM FOR ENCODING FOR 100G-KR NETWORKING - In one embodiment, a coding method that uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. | 07-12-2012 |
20140053042 | Communication device employing binary product coding with selective additional Cyclic Redundancy Check (CRC) therein - Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions. | 02-20-2014 |
20140173384 | METHOD AND SYSTEM FOR ENCODING FOR 100G-KR NETWORKING - Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block. | 06-19-2014 |
Patent application number | Description | Published |
20090196277 | WIRELESS NETWORK SYNCHRONIZATION - Systems and methodologies are described that facilitate synchronizing timing among wireless nodes in a wireless communication network. A tracking wireless node can synchronize to a global positioning system (GPS) signal if available. Alternatively, the tracking wireless node can receive quality metrics related to one or more target nodes. The quality metrics can relate to parameters that can be utilized to evaluate the target node for timing synchronization. Based on the quality metrics, the tracking wireless node can select a target wireless node for timing synchronization. The tracking wireless node can subsequently synchronize timing with the target wireless node. In addition, the tracking wireless node can continually evaluate surrounding wireless nodes to detect whether other wireless nodes have higher quality metrics than the current target wireless nodes and can accordingly resynchronize with nodes having higher metrics. | 08-06-2009 |
20100046494 | BASE STATION SYNCHRONIZATION - Systems and methodologies are described that facilitate synchronizing base stations in a wireless communication environment. A base station can receive a synchronization signal sent via a low reuse channel, which can be shared by a group of base stations. Further, the base station can align a clock associated therewith to the received synchronization signal. Moreover, the base station can coarsely align the clock to a first synchronization signal received upon a first subset of resources of the low reuse channel, and finely align the clock to a second synchronization signal received upon a second subset of resources (e.g., of the low reuse channel, of a separate channel, . . . ), where the second subset of resources can be reserved for transmission from at least one base station with at least a predetermined level of synchronous accuracy. | 02-25-2010 |
20120045024 | METHODS AND APPARATUS FOR ITERATIVE DECODING IN MULTIPLE-INPUT-MULTIPLE-OUTPUT (MIMO) COMMUNICATION SYSTEMS - Methods and apparatus for receiving, processing, and decoding MIMO transmissions in communications systems are described. A non-Gaussian approximation method for simplifying processing complexity where summations are used is described. Use of a priori information to facilitate determination of log likelihood ratios (LLRs) in receivers using iterative decoders is further described. A Gaussian or non-Gaussian approximation method using a priori information may be used to determine a K-best list of values for summation to generate an LLR is also described. | 02-23-2012 |
20120099446 | REPORTING OF CHANNEL QUALITY INDICATORS FOR A NON-LINEAR DETECTOR - Techniques for determining channel quality indicators (CQIs) for a non-linear detector at a user equipment (UE) are described. In one design, the UE may determine at least one parameter (e.g., at least one threshold) based on at least one constellation constrained capacity function. Each threshold may correspond to a maximum number of information bits for one stream when a particular modulation order is used for another stream. The UE may determine CQIs for multiple streams for the non-linear detector based on the at least one parameter. The UE may also select a precoding matrix (e.g., jointly with the CQIs) based on the at least one parameter. The UE may report the selected precoding matrix and the CQIs for the multiple streams. The UE may thereafter receive a transmission of the multiple streams, which may be transmitted based on the selected precoding matrix and the CQIs. | 04-26-2012 |
20140016677 | METHOD AND APPARATUS TO DYNAMICALLY SELECT UE PROCESSING CAPABILITIES BASED ON CHANNEL IMPULSE RESPONSE ESTIMATES - A method, an apparatus, and a computer program product for wireless communication are provided in connection with dynamic selection of a UE receiver. In one example, a communications device is equipped to obtain one or more channel impulse response (CIR) estimates, generate a delay spread metric value that characterizes a multipath delay spread of a channel based on the obtained one or more CIR estimates, and select a receiver option with a first power consumption value, for use by the UE, from a plurality receiver options with different optimal power consumption values, based on the generated delay spread metric value. In an aspect, a comparatively more complex receiver option may be selected when the channel is rich in multipath. In another aspect, a comparatively less complex receiver option may be selected when the channel exhibits flat fading. | 01-16-2014 |
Patent application number | Description | Published |
20120001354 | MAKING NANOSTRUCTURED POROUS HOLLOW SPHERES WITH TUNABLE STRUCTURE - Hollow, porous, spherical metal-carbon composite particles, having nanostructures, are prepared from suitable precursor solutions containing metal-organic ligand coordination complexes with template. Such precursors may be made for each elemental metal to be in the spherical particles. The precursor solution is atomized as an aerosol in an inert gas stream and the aerosol stream heated to decompose the organic ligand portion of the precursor leaving the spherical metal-carbon composite or metal alloy-carbon composite particles. The organic ligand serves as a structure directing agent in the shaping of the spherical particles after the ligand has been removed. Other materials may also be used as permanent or removed templates. The morphology of the particles may be altered for an application by varying the preparation and composition of the metal precursor material, and the optional use of a template. | 01-05-2012 |
20120001357 | MAKING NANOCRYSTALLINE MESOPOROUS SPHERICAL PARTICLES - Spherical particles of one or more elemental metals and carbon are prepared from a precursor in the form of a metal oleate. The metal oleate precursor is dispersed in a liquid vehicle and aerosol droplets of the dispersed precursor are formed in a stream of an inert gas. The aerosol droplets are heated in the stream to decompose the oleate ligand portion of the precursor and form spherical particles that have a mesoporous nanocrystalline structure. The open mesopores of the spherical particles provide a high surface area for contact with fluids in many applications. For example, the mesopores can be infiltrated with a hydrogen absorbing material, such as magnesium hydride, in order to increase the hydrogen storage capacity of the particles. | 01-05-2012 |
20130323595 | LITHIUM ION BATTERY ELECTRODE MATERIALS AND METHODS OF MAKING THE SAME - An example of a lithium ion battery electrode material includes a substrate, and a substantially graphitic carbon layer completely encapsulating the substrate. The substantially graphitic carbon layer is free of voids. Methods for making electrode materials are also disclosed herein. | 12-05-2013 |
Patent application number | Description | Published |
20110058279 | OVERCOAT HAVING A LOW SILICON/CARBON RATIO - A slider for an information storage system. The slider comprising a single overcoat layer, wherein the layer is deposited onto an ABS of the slider by a filtered cathodic arc process, the layer having a Si/C ratio less than about 10% and a thickness of less than about 15 Å. | 03-10-2011 |
20120012554 | SYSTEM AND METHOD OF FABRICATING MEDIA - A method of fabricating media comprises forming recording media on a substrate. An overcoat is deposited on the recording media opposite the substrate. The overcoat has a first surface finish. The overcoat is etched to remove material and provide the overcoat with a second surface finish that is smoother than the first surface finish. The depositing and etching may occur sequentially in an in-situ, dry vacuum process. The second surface finish may not be mechanically processed after etching to further planarize the overcoat. | 01-19-2012 |
20120325771 | SYSTEM AND METHOD OF FABRICATING MEDIA - A method of fabricating media comprises forming recording media on a substrate. An overcoat is deposited on the recording media opposite the substrate. The overcoat has a first surface finish. The overcoat is etched to remove material and provide the overcoat with a second surface finish that is smoother than the first surface finish. The depositing and etching may occur sequentially in an in-situ, dry vacuum process. The second surface finish may not be mechanically processed after etching to further planarize the overcoat. | 12-27-2012 |
20130094109 | SYSTEM, METHOD AND APPARATUS FOR ANTICORROSION OVERCOAT - A magnetic media disk has a substrate; a recording magnetic media on the substrate; and an overcoat on the recording magnetic media, the overcoat comprising a Si-based layer on the recording magnetic media, and a Ti-based layer on the Si-based layer. | 04-18-2013 |
20130235490 | Perpendicular magnetic recording media with seed layer structurecontaining ruthenium (Ru) - An embodiment of the invention provides an apparatus that includes: a perpendicular magnetic recording medium including a substrate, a soft under layer above the substrate, a seed layer structure above the soft under layer, wherein the seed layer structure contains Ruthenium; and a magnetic recording layer above the seed layer structure. | 09-12-2013 |
20130309526 | PLASMA POLISH FOR MAGNETIC RECORDING MEDIA - Fabrication methods for magnetic recording media that use a plasma polish are disclosed. For one exemplary method, a film of a magnetic recording medium is deposited, and a top surface of the film is polished utilizing a plasma formed by a noble gas to smoothen the top surface of the film. A subsequent layer is then deposited onto the polished top surface of the film. A top surface of the subsequent layer has a reduced roughness by being deposited on the polished top surface of the film. | 11-21-2013 |
Patent application number | Description | Published |
20090078927 | Composite hard mask for the etching of nanometer size magnetic multilayer based device - A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying free layer. The middle metallic spacer provides a height margin during subsequent processing to avoid shorting between a bit line and the MTJ cell in the final device. An upper conductive layer may be made of Ta and is thin enough to allow a MTJ pattern in a thin overlying photoresist layer to be transferred through the Ta during a fluorocarbon etch without consuming all of the photoresist. The MTJ pattern is transferred through the remaining hard mask layers and underlying MTJ stack of layers with a second etch step using a C, H, and O etch gas composition. | 03-26-2009 |
20090104718 | Method of magnetic tunneling layer processes for spin-transfer torque MRAM - A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions. | 04-23-2009 |
20090173977 | Method of MRAM fabrication with zero electrical shorting - An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O | 07-09-2009 |
20100109106 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 05-06-2010 |
20100123207 | Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication - A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer. | 05-20-2010 |
20110076785 | Process to fabricate bottom electrode for MRAM device - Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”. | 03-31-2011 |
20110101478 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 05-05-2011 |
20110129946 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 06-02-2011 |
20110133300 | Bottom electrode for MRAM device - A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer. | 06-09-2011 |
Patent application number | Description | Published |
20090045785 | SENSING A PHASE-PATH CURRENT IN A MULTIPHASE POWER SUPPLY SUCH AS A COUPLED-INDUCTOR POWER SUPPLY - An embodiment of a power supply includes a supply output node, phase paths, and sensor circuits. The supply output node is operable to carry a regulated output voltage, and each phase path has a respective phase-path non-output node, has a respective phase-path output node coupled to the supply output node, and is operable to carry a respective phase current. And each sensor circuit has a respective sensor node coupled to the phase-path non-output nodes and is operable to generate a respective sense signal that represents the phase current flowing through a respective one of the phase paths. For example, where the phase paths are magnetically coupled to one another, the sensor circuits take into account the portions of the phase currents induced by the magnetic couplings to generate sense signals that more accurately represent the phase currents as compared to conventional sensor circuits. | 02-19-2009 |
20140191738 | SENSING A PHASE-PATH CURRENT IN A COUPLED-INDUCTOR POWER SUPPLY - An embodiment of a power supply includes an output node, inductively coupled phase paths, and a sensor circuit. The output node is configured to provide a regulated output signal, and the inductively coupled phase paths are each configured to provide a respective phase current to the output node. And the sensor circuit is configured to generate a sense signal that represents the phase current flowing through one of the phase paths. For example, because the phase paths are inductively coupled to one another, the sensor circuit takes into account the portions of the phase currents induced by the inductive couplings to generate a sense signal that more accurately represents the phase current through a single phase path as compared to conventional sensor circuits. | 07-10-2014 |
Patent application number | Description | Published |
20110062926 | SYSTEM AND METHOD FOR CONTROLLING A VOLTAGE SUPPLY - A system, voltage supply circuit, control unit for a voltage supply circuit, and method of controlling a voltage supply circuit are disclosed. For example, a system is disclosed that comprises at least one electronic circuit and a voltage supply unit coupled to an input of the at least one electronic circuit. The voltage supply unit includes a power unit to supply a voltage to the at least one electronic circuit and a control unit to control an operating mode of the power unit, an output of the control unit coupled to an input of the power unit. The control unit includes a mode selector to select the operating mode of the power unit, coupled to at least a first output of the power unit, an amplifier coupled to the at least a first output of the power unit, a compensation circuit, and a first switching unit coupled to the mode selector and the compensation circuit, to couple the compensation circuit to the amplifier if a selected operating mode of the power unit is a first mode. | 03-17-2011 |
20140203790 | Hybrid Continuous and Discontinuous Mode Operation - This disclosure is directed to hybrid continuous and discontinuous mode operation. In general, a system comprising a control module and voltage converter module may be configured to operate in a continuous conduction mode (CCM) until a current through an inductor in the voltage converter module is determined to be at or below zero (e.g., negative). The controller may then transition to operating the voltage converter module in a discontinuous control mode (DCM). Some or all of the DCM may be implemented digitally within the controller. In this manner, benefits may be realized from operating in either CCM or DCM while minimizing the disadvantages associated with these control schemes. Moreover, digitizing DCM control may allow for easier implementation and better performance than traditional DCM operation. | 07-24-2014 |
Patent application number | Description | Published |
20100007533 | CAVLC RUN-BEFORE DECODING SCHEME - Techniques for decoding the run_before fields in a CAVLC encoded bitstream for H.264 are disclosed. In one aspect, the codewords corresponding to a plurality of consecutive initial zero-value run_before codewords are stored in a look-up table, allowing the decoding of such a plurality of run_before codewords in a single computation cycle. In another aspect, the look-up table is additionally configured to decode the next non-zero run_before value after the initial zero-value run_before codewords in the same computation cycle. | 01-14-2010 |
20100046627 | DECODING SYSTEM AND METHOD - Decoding systems and methods are disclosed. In a particular embodiment, a video decoder system includes a first decoding path and a second decoding path configured to decode at a slower average rate than the first decoding path. The video decoder system includes a dynamic switch configured to provide a first portion of the encoded video signal to the first decoding path or to the second decoding path. The dynamic switch is further configured to provide a subsequent portion of the encoded video signal to the first decoding path or to the second decoding path in response to a value of a decoding metric associated with decode processing of the first portion. | 02-25-2010 |
20100086057 | METHOD AND APPARATUS FOR REDUCING BUS TRAFFIC OF A TEXTURE DECODING MODULE IN A VIDEO DECODER - Techniques for reducing bus traffic during texture decoding of a video bitstream are provided. In one configuration, a wireless communication device (e.g., cellular phone, etc.) comprises a processor configured to execute instructions operative to decode and separate in a bitstream macroblock (MB) information and residual packet data. The residual packet data is used to generate codec-independent non-zero MB-packets having a universal order that is codec independent. The codec-independent non-zero MB-packets and MB information are then used for reconstructing pixels of a respective frame of the video bitstream. | 04-08-2010 |
20130188701 | SUB-BLOCK LEVEL PARALLEL VIDEO CODING - The techniques of this disclosure are generally related to parallel coding of video units that reside along rows or columns of blocks in largest coding units. For example, the techniques include removing intra-prediction dependencies between two video units in different rows or columns to allow for parallel coding of rows or columns of the video units. | 07-25-2013 |
20130188732 | Multi-Threaded Texture Decoding - A method for performing texture decoding in a multi-threaded processor includes substantially simultaneously decoding, in multiple hardware threads, at least two macro-blocks of a VP8 frame. Each hardware thread decodes one macro-block at a time. The method may also include assigning a macro-block from the at least two macro-blocks of the VP8 frame to a hardware thread of the multi-threaded processor. | 07-25-2013 |
20140169483 | DEBLOCKING FILTER WITH REDUCED LINE BUFFER - An apparatus configured to filter video information according to certain aspects includes a memory unit and a processor in communication with the memory unit. The memory unit stores video information comprising at least two adjacent video blocks, each video block comprising a plurality of video samples, and each video sample having a bit depth. The processor determines a filtered video sample based at least in part on a video sample and an adjustment value. The processor determines the adjustment value at least in part from an input with a limited bit depth. The input is determined from a set of one or more video samples, and its bit depth is limited such that it is less than the bit depth of the one or more video samples. | 06-19-2014 |
20150022677 | SYSTEM AND METHOD FOR EFFICIENT POST-PROCESSING VIDEO STABILIZATION WITH CAMERA PATH LINEARIZATION - Described herein are methods, systems, and apparatus to process video images to remove jitteriness due to hand shake. In one aspect, a camera is configured to capture raw video composed of a series of successive image frames of a scene of interest. A processor is configured to receive the image frames, estimate a global camera motion from successive frames, stabilize the camera motion by establishing an upper bound and a lower bound of the global camera motion and smoothing the curve of camera motion between the upper and lower bounds, and upsample the resulting stabilized video frames to produce a smooth video. | 01-22-2015 |
Patent application number | Description | Published |
20110132867 | METHOD AND SYSTEM FOR IMPRINT LITHOGRAPHY - A method and apparatus of imprint lithography wherein the method includes depositing a material on a patterned surface of a conductive substrate, and pressing a transparent substrate and the conductive substrate together, wherein the pressing causes the material to conform to the patterned surface. Energy is applied to the material to form patterned material from the material. The transparent substrate and the conductive substrate are separated, wherein the patterned material adheres to the transparent substrate. | 06-09-2011 |
20120082866 | PATTERNED TEMPLATE WITH 1xN NUCLEATION SITE TO GRAIN GROWTH FOR UNIFORM GRAIN SIZE RECORDING MEDIA - A perpendicular magnetic media includes a substrate, a patterned template, a seed layer and a magnetic layer. The patterned template is formed on the substrate and includes a plurality of growth sites that are evenly spaced apart from each other. The seed layer is formed over the patterned template and the exposed areas of the substrate. Magnetic material is sputter deposited onto the seed layer with one grain of the magnetic material nucleated over each of the growth sites. The grain size distribution of the magnetic material is reduced by controlling the locations of the growth sites which optimizes the performance of the perpendicular magnetic media. | 04-05-2012 |
20120107583 | BLOCK COPOLYMER SELF-ASSEMBLY METHODS AND PATTERNS FORMED THEREBY - Patterned substrates templates are provided, as well as methods comprising a combination of lithography and self-assembly techniques. The patterned substrates may comprise first and second patterns. | 05-03-2012 |
20120135159 | SYSTEM AND METHOD FOR IMPRINT-GUIDED BLOCK COPOLYMER NANO-PATTERNING - This disclosure describes a method for nano-patterning by incorporating one or more block copolymers and one or more nano-imprinting steps in the fabrication process. The block copolymers may be comprised of organic or organic components, and may be lamellar, spherical or cylindrical. As a result, a patterned medium may be formed having one-dimensional or two-dimensional patterns with a feature pitch of 5-100 nm and/or a bit density of at least 1 Tdpsi. | 05-31-2012 |
20120164389 | IMPRINT TEMPLATE FABRICATION AND REPAIR BASED ON DIRECTED BLOCK COPOLYMER ASSEMBLY - Imprinted apparatuses, such as Bit-Patterned Media (BPM) templates, Discrete Track Recording (DTR) templates, semiconductors, and photonic devices are disclosed. Methods of fabricating imprinted apparatuses using a combination of patterning and block copolymer (BCP) self-assembly techniques are also disclosed. | 06-28-2012 |
20130186856 | METHOD OF FABRICATING SERVO INTEGRATED TEMPLATE - The embodiments disclose a method of fabricating servo integrated templates including depositing a protective layer on servo zone resist layer patterns, patterning integrated data zone features into a substrate, depositing a protective layer on data zones and removing the servo zone protective layer and patterning integrated servo zone features into the substrate and removing the data zone protective layer creating a substrate template used in fabricating data and servo zone integrated patterned stacks. | 07-25-2013 |
20140127533 | PATTERNED TEMPLATE WITH 1xN NUCLEATION SITE TO GRAIN GROWTH FOR UNIFORM GRAIN SIZE RECORDING MEDIA - A perpendicular magnetic media includes a substrate, a patterned template, a seed layer and a magnetic layer. The patterned template is formed on the substrate and includes a plurality of growth sites that are evenly spaced apart from each other. The seed layer is formed over the patterned template and the exposed areas of the substrate. Magnetic material is sputter deposited onto the seed layer with one grain of the magnetic material nucleated over each of the growth sites. The grain size distribution of the magnetic material is reduced by controlling the locations of the growth sites which optimizes the performance of the perpendicular magnetic media. | 05-08-2014 |
20150017481 | BIT PATTERNED GROWTH GUIDING MECHANISM - The embodiments disclose a structure, including a first layer selectively etched on a substrate with a seedlayer deposited thereon, a first layer bit patterned growth guiding mechanism on the seedlayer, and a plurality of bit patterned magnetic recording features grown on the seedlayer guided by the growth guiding mechanism. | 01-15-2015 |
Patent application number | Description | Published |
20090222574 | Trust Information Delivery Scheme for Certificate Validation - A unique TIO based trust information delivery scheme is disclosed that allows clients to verify received certificates and to control Java and Javascript access efficiently. This scheme fits into the certificate verification process in SSL to provide a secure connection between a client and a Web server. In particular, the scheme is well suited for incorporation into consumer devices that have a limited footprint, such as set-top boxes, cell phones, and handheld computers. Furthermore, the TIO update scheme disclosed herein allows clients to update certificates securely and dynamically. | 09-03-2009 |
20120023328 | Trust Information Delivery Scheme for Certificate Validation - A unique TIO based trust information delivery scheme is disclosed that allows clients to verify received certificates and to control Java and Javascript access efficiently. This scheme fits into the certificate verification process in SSL to provide a secure connection between a client and a Web server. In particular, the scheme is well suited for incorporation into consumer devices that have a limited footprint, such as set-top boxes, cell phones, and handheld computers. Furthermore, the TIO update scheme disclosed herein allows clients to update certificates securely and dynamically. | 01-26-2012 |
20130283042 | Trust Information Delivery Scheme for Certificate Validation - A unique TIO based trust information delivery scheme is disclosed that allows clients to verify received certificates and to control Java and Javascript access efficiently. This scheme fits into the certificate verification process in SSL to provide a secure connection between a client and a Web server. In particular, the scheme is well suited for incorporation into consumer devices that have a limited footprint, such as set-top boxes, cell phones, and handheld computers. Furthermore, the TIO update scheme disclosed herein allows clients to update certificates securely and dynamically. | 10-24-2013 |
Patent application number | Description | Published |
20080294758 | METHODS AND APPARATUSES FOR ADJUSTING BANDWIDTH ALLOCATION DURING A COLLABORATION SESSION - In one embodiment, the systems and methods determine an initial bandwidth at a client device; allocate an allocated bandwidth to the client device between a first server and a second server; monitor the allocated bandwidth; and adjust the allocated bandwidth based on a target bandwidth from the first server to the client. | 11-27-2008 |
20100005142 | REAL-TIME EVENT NOTIFICATION FOR COLLABORATIVE COMPUTING SESSIONS - In one embodiment, a determination is made that a specified event of a collaborative computing session has occurred. In response to the specified event, a real-time electronic notification is transmitted to a particular set of one or more attendees of the session that the event has occurred, the notification illustratively transmitted via a communication channel other than the session. | 01-07-2010 |
20100088414 | SELECTIVELY JOINING CLIENTS TO MEETING SERVERS - In an embodiment, a hosted-on-premises meeting exchange server operates seamlessly with web meeting servers. For example, one computer-implemented method comprises receiving a request from a client computer to join a web meeting; determining whether the client computer is coupled to a local network which includes an on-premises-meeting exchange server; in response to determining that the client computer is coupled to the local network, joining the client computer to the web meeting at the on-premises-meeting exchange server when the on-premises-meeting exchange server has sufficient capacity, and otherwise joining the client computer to the web meeting at an off-premises-meeting exchange server; and in response to determining that the client computer is not coupled to the local network, joining the client computer to the web meeting at the off-premises-meeting exchange server. | 04-08-2010 |
20110023096 | TOKEN-BASED CONTROL OF PERMITTED SUB-SESSIONS FOR ONLINE COLLABORATIVE COMPUTING SESSIONS - In one embodiment, a client device may send one or more sub-session requests to one or more corresponding session controllers through a computer network to obtain one or more corresponding sub-session tokens that indicate in which sub-sessions of an online collaborative computing session the client device is permitted to participate. The client device may then receive particular sub-session tokens (e.g., based on certain permissions), which may then be sent to a collaboration server to establish one or more permitted sub-sessions of the online collaborative computing session with the client device as indicated by the received sub-session tokens. | 01-27-2011 |
20110276635 | METHODS AND APPARATUSES FOR ADJUSTING BANDWIDTH ALLOCATION DURING A COLLABORATION SESSION - In one embodiment, a participant device joins a collaboration session among a plurality of participant devices. The content shared within the collaboration session includes lower-priority data and higher-priority data. An initial available bandwidth for use with the collaboration session is determined. Based on the initial available bandwidth and an expected second bandwidth for higher-priority data shared within the collaboration session, a first bandwidth is allocated for lower-priority data shared within the collaboration session. During the collaboration session, an actual second bandwidth for the higher-priority data shared within the collaboration session is monitored. The expected second bandwidth is compared to the monitored actual second bandwidth, and a bandwidth variant is determined. Based on the determined bandwidth variant, the first bandwidth allocated for the lower-priority data shared within the collaboration session is adjusted to increase the bandwidth allocated for the lower-priority data. | 11-10-2011 |
Patent application number | Description | Published |
20090135370 | Magnetic locker for spectacle frame - A locker of a spectacle frame, adapted for connecting a first member and a second member of the spectacle frame, includes a receiving portion, an inserting portion and a locking mechanism. The receiving portion is adapted for providing at an end of the first member of the spectacle frame. The inserting portion, which is adapted for providing at an end of the second member of the spectacle frame, is arranged to be freely slide into the receiving portion. The locking mechanism includes a locking member movably disposed between the receiving portion and the inserting portion as a locking position to lock up the inserting portion from being detached from the receiving portion. The locking member is able to be driven from the locking position to an unlocking position that the inserting portion is able to be slid out of the receiving portion for separating the first and second members. The locker can be used in spectacle frame for exchanging and adjusting temples, end-pieces, hinges as well as the bridge. | 05-28-2009 |
20110304813 | Apparatus for of rimless spectacles - A pair of rimless spectacles comprises a pair of lenses, a pair of temple units and a bridge. Each lens includes at least two open slots that provided at a predetermined location and an open recess is formed on top of each open slot on the rear side of the lens. The open recess has a declined surface declining from the peripheral edge toward to inner portion of the lens. Each temple unit includes at least one fasten apparatus and the bridge has two, when each fasten apparatuses of each temple units and the bridge has been inserted into the open slot and the open recess of each lenses respectively, the lenses can be securely locked up by the fasten apparatus to form a pair of rimless spectacles while the declined surface of the open recess will block and prevent the fasten apparatus moving out from the lens. | 12-15-2011 |
20120257160 | Rim-locker for spectacle frame - A rim locker for spectacle frame comprises a first portion and a second portion which are connected to two edges of lens rim in cut-off position respectively. The second portion has a screw hole for inserting a screw and the first portion is having thread to let the screw in for fastening the lens rim. The screw further has a stopping cap and the first portion further has a cylinder housing for hiding and moving the stopping cap, so that when the rim-locker is opening, the stopping cap will moving along the track of the housing, and stop at the end to prevent the screw slip off from the rim-locker and protect the screw threads not strip off easily. | 10-11-2012 |
20120281180 | Rimless eyeglass frame - A pair of rimless s eyeglass frame which comprising a pair of lenses, a pair of temple units and a bridge, wherein each lens has at least one slot with a blocking surface that is provided at a predetermined location of the lenses to engage with the press element of the fasten apparatuses that connected to the temple units or the bridge, so as to securely mount the temple units and the bridge onto the lenses to form a pair of rimless eyeglass frame. | 11-08-2012 |
Patent application number | Description | Published |
20080200485 | Kinase Inhibitors - Disclosed are protein kinase inhibitors, compositions comprising such inhibitors, and methods of use, thereof. More particularly, disclosed are inhibitors of Aurora-2 (Aurora-A) protein kinase. Also disclosed are methods of treating diseases associated with protein kinases, especially diseases associated with Aurora-2, such as cancer. | 08-21-2008 |
20090264422 | METHOD OF TREATING DISEASE STATES USING SUBSTITUTED PYRAZOLE COMPOUNDS - Disclosed are protein kinase inhibitors, compositions comprising such inhibitors, and methods of use thereof. More particularly, disclosed are inhibitors of Aurora A (Aurora-2) protein kinase. Also disclosed are methods of treating diseases associated with protein kinases, especially diseases associated with Aurora-2, such as cancer. | 10-22-2009 |
20100105671 | C7-fluoro substituted tetracycline compounds - The present invention is directed to a compound represented by Structural Formula (A): | 04-29-2010 |
20110212857 | Multiplexed Assay Using Encoded Solid Support Matrices - In a multiplexed assay, each molecule of a plurality of molecules is attached to a support matrix with a substrate adapted for attachment and/or synthesis of molecules and an integrally-formed memory device with an optically-encoded identifier to uniquely identify the molecule attached to the substrate. The molecules are exposed to one or more processing conditions then placed within the path of an optical detector adapted to read the optically-encoded identifier and measure biochemical processes on each support matrix. The support matrices may besingulated to be read by the optical detector one at a time. | 09-01-2011 |
20110237459 | Multiplexed Assay Using Encoded Solid Support Matrices - In a multiplexed assay, each molecule of a plurality of molecules is attached to a support matrix with a substrate adapted for attachment and/or synthesis of molecules and an integrally-formed memory device with an optically-encoded identifier to uniquely identify the molecule attached to the substrate. The molecules are exposed to one or more processing conditions then placed within the path of an optical detector adapted to read the optically-encoded identifier and measure biochemical processes on each support matrix. The support matrices may be singulated to be read by the optical detector one at a time. | 09-29-2011 |
20110269714 | Polycyclic Tetracycline Compounds - The present invention is directed to a compound represented by Structural Formula (I): | 11-03-2011 |
20120108569 | 8-AZA Tetracycline Compounds - The present invention is directed to a compound represented by Structural Formula (I) or a pharmaceutically acceptable salt thereof. The variables for Structural Formula I are defined herein. Also described is a pharmaceutical composition comprising the compound of Structural Formula I and its therapeutic use. | 05-03-2012 |
20120115819 | Pentacycline Compounds - The present invention is directed to a compound represented by Structural Formula (I): or a pharmaceutically acceptable salt thereof. The variables for Structural Formula (I) are defined herein. Also described is a pharmaceutical composition comprising the compound of Structural Formula (I) and its therapeutic use. | 05-10-2012 |
20120135968 | Tetracycline Compounds - The present invention is directed to a compound represented by Structural Formula (I): or a pharmaceutically acceptable salt thereof. The variables for Structural Formula I are defined herein. Also described is a pharmaceutical composition comprising the compound of Structural Formula I and its therapeutic use. | 05-31-2012 |
20120208788 | Tetracycline Compounds - The present invention is directed to a compound represented by Structural Formula (1): or a pharmaceutically acceptable salt thereof. The variables for Structural Formula (I) are defined herein. Also described is a pharmaceutical composition comprising the compound of Structural Formula (I) and its therapeutic use. | 08-16-2012 |
20120238466 | Multiplexed Assay Using Encoded Solid Support Matrices - In a multiplexed assay, each molecule of a plurality of molecules is attached to a support matrix with a substrate adapted for attachment and/or synthesis of molecules and an integrally-formed memory device with an optically-encoded identifier to uniquely identify the molecule attached to the substrate. The molecules are exposed to one or more processing conditions then placed within the path of an optical detector adapted to read the optically-encoded identifier and measure biochemical processes on each support matrix. The support matrices may be singulated to be read by the optical detector one at a time. | 09-20-2012 |
20120302527 | C7-Fluoro Substituted Tetracycline Compounds - The present invention is directed to a compound represented by Structural Formula (A): | 11-29-2012 |
Patent application number | Description | Published |
20140076965 | AUGMENTED REALITY MESSAGING SYSTEM AND METHOD BASED ON MULTI-FACTOR RECOGNITION - Enables creating, displaying, and managing augmented reality (AR) messages linked to objects that display or contain identifiable information such as codes, including card products/prepaid card products, etc. Applies multi-factor recognition technology to process an object/card having a unique code. May utilize an application on a mobile device/computer, to capture an image of the object, recognize the signature of the object, convert the code into alphanumeric digits and generate a Unique Identification Token (UIT). The application can create a personalized AR message, e.g., text, 2D/3D image, freehand drawing, animation, video, audio, avatar character, or any combination, optionally enhanced with pre-made templates. The completed message is stored in a remote database with the UIT. The recipient of the object/card uses the application and captures an image of the object or card image with code, triggering the message experience that may display account balance information and targeted advertising. | 03-20-2014 |