Patent application number | Description | Published |
20140177325 | INTEGRATED MRAM MODULE - Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability. | 06-26-2014 |
20140201435 | HETEROGENEOUS MEMORY SYSTEMS, AND RELATED METHODS AND COMPUTER-READABLE MEDIA FOR SUPPORTING HETEROGENEOUS MEMORY ACCESS REQUESTS IN PROCESSOR-BASED SYSTEMS - Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage. | 07-17-2014 |
20140237160 | INTER-SET WEAR-LEVELING FOR CACHES WITH LIMITED WRITE ENDURANCE - A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N | 08-21-2014 |
20140237191 | METHODS AND APPARATUS FOR INTRA-SET WEAR-LEVELING FOR MEMORIES WITH LIMITED WRITE ENDURANCE - Efficient techniques are described for extending the usable lifetime for memories with limited write endurance. A technique for wear-leveling of caches addresses unbalanced write traffic on cache lines which cause heavily written cache lines to fail much fast than other lines in the cache. A counter is incremented for each write operation to a cache array. A line affected by a current write operation which caused the counter to meet a threshold is evicted from the cache rather than writing data to the affected line. A dynamic adjustment of the threshold can be made depending on the operating program. Updates to a current replacement policy pointer are stopped due to the counter meeting the threshold. | 08-21-2014 |
20140258636 | CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS - Critical-word-first reordering of cache fills to accelerate cache memory accesses, and related processor-based systems and methods are disclosed. In this regard in one embodiment, a cache memory is provided. The cache memory comprises a data array comprising a cache line, which comprises a plurality of data entry blocks configured to store a plurality of data entries. The cache memory also comprises cache line ordering logic configured to critical-word-first order the plurality of data entries into the cache line during a cache fill, and to store a cache line ordering index that is associated with the cache line and that indicates the critical-word-first ordering of the plurality of data entries in the cache line. The cache memory also comprises cache access logic configured to access each of the plurality of data entries in the cache line based on the cache line ordering index for the cache line. | 09-11-2014 |
20140281184 | MIXED MEMORY TYPE HYBRID CACHE - A hybrid cache includes a static random access memory (SRAM) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both SRAM macros and resistive random access memory macros. The hybrid cache is configured so that the SRAM macros are accessed before the resistive random memory macros in each cache access cycle. While SRAM macros are accessed, the slower resistive random access memory reach a data access ready state. | 09-18-2014 |
20140281327 | SYSTEM AND METHOD TO DYNAMICALLY DETERMINE A TIMING PARAMETER OF A MEMORY DEVICE - A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter. | 09-18-2014 |
Patent application number | Description | Published |
20140379978 | REFRESH SCHEME FOR MEMORY CELLS WITH WEAK RETENTION TIME - A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address. | 12-25-2014 |
20150016203 | DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION - A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank. | 01-15-2015 |
20150016204 | INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES - A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations. | 01-15-2015 |
20150085594 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information. | 03-26-2015 |
20150092479 | RESISTANCE-BASED MEMORY CELLS WITH MULTIPLE SOURCE LINES - In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value. | 04-02-2015 |
20150121006 | SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE - A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command. | 04-30-2015 |
20150134897 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device. | 05-14-2015 |
20150149865 | CACHE STRUCTURE WITH PARITY-PROTECTED CLEAN DATA AND ECC-PROTECTED DIRTY DATA - A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache. | 05-28-2015 |
20150162065 | REFRESH SCHEME FOR MEMORY CELLS WITH NEXT BIT TABLE - A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address. | 06-11-2015 |
20150186198 | BIT REMAPPING SYSTEM - A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element. | 07-02-2015 |
20150186279 | SYSTEM AND METHOD TO DEFRAGMENT A MEMORY - A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address. | 07-02-2015 |
20150243373 | KERNEL MASKING OF DRAM DEFECTS - Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold. | 08-27-2015 |
20150310904 | SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY - In a memory having a first memory cell array, a second memory cell array, an address is received on an address port. Based on the address, an internal address is transmitted, and it is latched and held for a first interval as a first array address. The first memory cell array is accessed over the first interval, based on the first array address. Another address is received at the address port, during the first interval, and another internal address is transmitted, and latched and held for a second interval that overlaps the first interval, as a second array address. The second memory cell array is accessed during the second interval, based on the second array address. | 10-29-2015 |
20150318035 | PRIORITY ADJUSTMENT OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) TRANSACTIONS PRIOR TO ISSUING A PER-BANK REFRESH FOR REDUCING DRAM UNAVAILABILITY - Priority adjustment of dynamic random access memory (DRAM) transactions prior to issuing a per-bank refresh for reducing DRAM unavailability is disclosed. In one aspect, DRAM is refreshed on a per-bank basis. If a queued memory transaction corresponds to a memory bank that will soon be refreshed, the transaction may be delayed if a refresh of the corresponding memory bank begins prior to execution of the transaction. To avoid delaying execution of the transaction while waiting for the corresponding memory bank to be refreshed, a priority of the memory transactions may be adjusted based on a memory bank refresh schedule. The priority of the transaction corresponding to the memory bank to be refreshed may be increased, and the priority of other memory transactions may be decreased, if such an adjustment would avoid or reduce delaying execution due to unavailability of the corresponding memory bank. | 11-05-2015 |
20150318057 | VARIABLE READ DELAY SYSTEM - A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay. | 11-05-2015 |
20150331623 | METHOD AND APPARATUS FOR USING A DEFECTIVE DYNAMIC READ-ONLY MEMORY REGION - Methods and apparatus for using a defective dynamic read-only memory region are provided. In an example, a defective Dynamic Random Access Memory (DRAM) page is used, instead of being disabled. A compress-and-store technique uses a non-defective region of a defective DRAM page to store page-swapping data. This allows the defective DRAM page to be used as a fast swapping resource, which results in increasing system performance, saving materials, saving time, and saving energy. In an example, a method for using a defective DRAM page in a DRAM includes using an error history table to determine that the defective DRAM page has a defective block, and updating a defect table with an address of the defective block. The defect table is used to determine an address of a good block in the defective DRAM page. Page swap data is compressed and stored in the good block in the defective DRAM page. | 11-19-2015 |
20150332750 | HYBRID MAGNETORESISTIVE READ ONLY MEMORY (MRAM) CACHE MIXING SINGLE-ENDED AND DIFFERENTIAL SENSING - A hybrid cache architecture uses magnetoresistive random-access memory (MRAM) caches but has two different types of bit cell sensing. One type of bit cell sensing is single-ended and the other type of bit cell sensing is differential. The result is a uniform bit cell array but a non-uniform sense amplifier configuration. | 11-19-2015 |
20160092355 | SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE - A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command. | 03-31-2016 |
Patent application number | Description | Published |
20110197238 | SYSTEM AND METHOD FOR IMPLEMENTING MEDIA INTERACTION OF THE IPTV - The present invention provides a method and a system for implementing media interaction of the IPTV. The method includes: a user terminal sending a request for a TVOD media file or a TSTV media file to a marginal stream media server in a marginal P2P area in which it resides; the marginal stream media server which is requested sending the first data block of a target media file to the user terminal; the user terminal playing the first data block of the target media file immediately after receiving the first data block of the target media file, at the same time, requesting a content delivery network agent in a P2P area of a terminal side in which the user terminal resides for an information list of content delivery network nodes capable of providing subsequent data blocks of the target media file; the content delivery network agent returning the information list of content delivery network nodes capable of providing the subsequent data blocks to the user terminal; the user terminal requesting to download and play the subsequent data blocks of the target media file. The present invention possesses advantages of high service quality, mitigating the pressure on the center stream media server and the marginal stream media server, and reducing the construction cost of the system | 08-11-2011 |
20110223954 | Radio resource mapping method - A resource mapping method is provided, in which a wireless communication system maps subcarriers to resource units through external permutation and internal permutation, the external permutation comprises: performing the first permutation on n physical resource units in every N | 09-15-2011 |
20110268070 | Resource Mapping Methods for Control Channels - The present invention provides resource mapping methods for control channels, wherein a method includes: a broadcast control channel is positioned in a frequency partition which includes one or a plurality of distributed resource units; and the start position of the broadcast control channel is arranged to be in the first distributed resource unit of the frequency partition. The technical solutions of the present invention solve the problems of the resource locations which are occupied by the control channels and the manner thereof, improve the performance of the control channels, enable the control channels to meet various requirements in the related technologies, such as a low bit error rate, resource mapping and interference suppression in the OFDMA system and the like, and ensure the spectrum efficiency of the wireless communication system based on the OFDMA technology. | 11-03-2011 |
20120263132 | METHOD FOR ENCODING RESOURCE INDEXES IN WIRELESS COMMUNICATION SYSTEM, AND BASE STATION - A method for encoding resource indexes in a wireless communication system, and a base station are provided in the present invention. The method comprises: a base station dividing L logical resource units into M resource allocation units, wherein M<=L, L<=N, and N is the number of physical resource units; and the base station transmitting indication information to a terminal, wherein the indication information indicates the resource allocation units that the base station assigns to the terminal from the M resource allocation units. The present invention achieves more flexible scheduling and allocation. | 10-18-2012 |
Patent application number | Description | Published |
20130330367 | COMPOSITIONS WITH ENHANCED IMMUNOGENICITY AND/OR REDUCED REACTOGENICITY - The present invention relates to improved vaccines and the design and making of such vaccines that enhance immunogenicity of the vaccine and/or reduce reactogenicity to the vaccine when administered. In particular the vaccines and immunogenic compositions of the present invention relate to flagellin-antigen fusion proteins in which the spatial orientation of the flagellin to antigen and the charge distribution of the antigen is optimized to enhance immunogenicity and/or reduce reactogenicity. The present invention also relates to methods of evaluating the vaccines by measuring the relative expression of certain gene markers. Altered expression of the genes relative to flagellin control sample may indicate that the vaccine is suitable to stimulate an adaptive immune response to the antigen component in the subject with minimal side effects. | 12-12-2013 |
20140065177 | FUSION PROTEINS AND METHODS OF USE - Compositions that include a fusion protein comprising flagellin and at least one antigen that has an isoelectric point greater than about 7.0 and that is fused to at least one domain 3 of the flagellin activate Toll-like Receptor 5. Methods of stimulating an immune response, in particular, a protective immune response include administering a composition that includes an antigen fused to a loop of domain 3 of flagellin. | 03-06-2014 |
20140235836 | Immunologic Constructs and Methods - The present invention relates to improved vaccines and the design and making of such vaccines that enhance immunogenicity of the vaccine and/or reduce reactogenicity to the vaccine when administered. In particular the vaccines and immunogenic compositions of the present invention relate to flagellin-antigen fusion proteins in which the spatial orientation of the flagellin to antigen and the charge distribution of the antigen is optimized to enhance immunogenicity and/or reduce reactogenicity and/or improve folding of the protein. | 08-21-2014 |
20140255438 | FUSION PROTEINS AND METHODS OF USE - Compositions that include a fusion protein comprising flagellin and at least one antigen that has an isoelectric point greater than about 7.0 and that is fused to at least one domain 3 of the flagellin activate Toll-like Receptor 5. Methods of stimulating an immune response, in particular, a protective immune response include administering a composition that includes an antigen fused to a loop of domain 3 of flagellin. | 09-11-2014 |
20150110827 | FUSION PROTEINS AND METHODS OF USE - Compositions that include at least three fusion proteins comprising flagellin and influenza antigens. In embodiments, the influenza antigens can include influenza A and influenza B antigens. The composition can further include at least one adjuvant. | 04-23-2015 |
Patent application number | Description | Published |
20110308627 | METHOD OF AND COMPUTER PROGRAM FOR MANAGING ONE OR MORE AGRICULTURAL DEVICES - A system and method for managing an agricultural device, including connecting the agricultural device to a network, collecting operational data relating to the agricultural device, granting an access right in respect of the collected operational data to an entity connected to the network, receiving data from the entity in response to the access right, and managing the agricultural device on the basis of the collected operational data and the data from the entity. The method may be implemented for managing multiple agricultural devices, and may be implemented in a computer readable medium. In one embodiment, the operational data relates to clinical mastitis detection. | 12-22-2011 |
20130269618 | SYSTEM AND METHOD FOR AUTOMATICALLY DETERMINING ANIMAL POSITION AND ANIMAL ACTIVITY - Monitoring activity of an animal in a system for housing freely moving animals including a plurality of animal ID stations, includes the steps of a) recording a first visit of said animal at a first of said animal ID stations, b) recording a subsequent second visit of said animal at a second of said animal ID stations, and c) determining a distance covered by said animal as the distance between said first animal ID station at said first visit and said second animal ID station at said second visit. With such simple means, parts of which are already present in e.g. most robot dairy stables, important information about activity of animals can easily be gathered. | 10-17-2013 |
20150339522 | METHOD OF AND ANIMAL TREATMENT SYSTEM FOR PERFORMING AN ANIMAL RELATED ACTION ON AN ANIMAL PART IN AN ANIMAL SPACE - A method determining a position of an animal part in an animal space in at least one direction, including: obtaining a two-dimensional image containing depth information; preprocessing the image according to first and second preprocessing modes, to provide respective first and second preprocessed images; comparing the first preprocessed image and the second preprocessed image to obtain at least one image difference; if the at least one image difference is below or equal to a respective predetermined threshold, processing the first preprocessed image according to a first position determining mode, and if the at least one image difference is above the predetermined threshold, processing the second preprocessed image according to a second position determining mode, to provide the position of the animal part. If a fast but not very accurate processing mode, and a slower but more accurate mode, are available, the method can suitably select one of these modes. | 11-26-2015 |